Changes between Version 2 and Version 3 of GcnInstrsSmem


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Timestamp:
Jun 9, 2017, 6:00:27 AM (21 months ago)
Author:
trac
Comment:

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  • GcnInstrsSmem

    v2 v3  
    33#!html
    44<h2>GCN ISA SMEM instructions (GCN 1.2)</h2>
    5 <p>The basic encoding of the SMEM instructions needs 9 bytes (2 dwords). List of fields:</p>
     5<p>The encoding of the SMEM instructions needs 8 bytes (2 dwords). List of fields:</p>
    66<table>
    77<thead>
     
    5656</ul>
    5757<p>For S_LOAD_DWORD* instructions, 2 SBASE SGPRs holds an base 48-bit address and a
    58 16-bit size.
    59 For S_BUFFER_LOAD_DWORD* instructions, 4 SBASE SGPRs holds a buffer descriptor.
    60 In this case, SBASE must be a multipla of 2.</p>
     5816-bit size. For S_BUFFER_LOAD_DWORD* instructions, 4 SBASE SGPRs holds a
     59buffer descriptor. In this case, SBASE must be a multipla of 2.
     60S_STORE_* and S_BUFFER_STORE_* accepts only M0 as offset register.</p>
    6161<p>The SMEM instructions can return the result data out of the order. Any SMEM operation
    6262(including S_MEMTIME) increments LGKM_CNT counter. The best way to wait for results