Changes between Initial Version and Version 1 of GcnInstrsSmrd


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Timestamp:
11/18/15 22:00:22 (8 years ago)
Author:
trac
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  • GcnInstrsSmrd

    v1 v1  
     1[wiki:ClrxToc Back to Table of content]
     2{{{
     3#!html
     4<h2>GCN ISA SMRD instructions</h2>
     5<p>The basic encoding of the SMRD instructions needs 4 bytes (dword). List of fields:</p>
     6<table>
     7<thead>
     8<tr>
     9<th>Bits</th>
     10<th>Name</th>
     11<th>Description</th>
     12</tr>
     13</thead>
     14<tbody>
     15<tr>
     16<td>0-7</td>
     17<td>OFFSET</td>
     18<td>Unsigned 8-bit dword offset or SGPR number that holds byte offset</td>
     19</tr>
     20<tr>
     21<td>8</td>
     22<td>IMM</td>
     23<td>IMM indicator</td>
     24</tr>
     25<tr>
     26<td>9-14</td>
     27<td>SBASE</td>
     28<td>Number of aligned SGPR pair.</td>
     29</tr>
     30<tr>
     31<td>15-21</td>
     32<td>SDST</td>
     33<td>Scalar destination operand</td>
     34</tr>
     35<tr>
     36<td>22-26</td>
     37<td>OPCODE</td>
     38<td>Operation code</td>
     39</tr>
     40<tr>
     41<td>27-31</td>
     42<td>ENCODING</td>
     43<td>Encoding type. Must be 0b11000</td>
     44</tr>
     45</tbody>
     46</table>
     47<p>Value of the IMM determines meaningful of the OFFSET field:</p>
     48<ul>
     49<li>IMM=1 - OFFSET holds a dword offset to SBASE.</li>
     50<li>IMM=0 - OFFSET holds number of SGPR that holds byte offset to SBASE.</li>
     51</ul>
     52<p>For S_LOAD_DWORD<em> instructions, 2 SBASE SGPRs holds an base 48-bit address and a
     5316-bit size.
     54For S_BUFFER_LOAD_DWORD</em> instructions, 4 SBASE SGPRs holds a buffer descriptor.
     55In this case, SBASE must be a multipla of 2.</p>
     56<p>List of the instructions by opcode:</p>
     57<table>
     58<thead>
     59<tr>
     60<th>Opcode</th>
     61<th>Mnemonic (GCN1.0)</th>
     62<th>Mnemonic (GCN1.0)</th>
     63</tr>
     64</thead>
     65<tbody>
     66<tr>
     67<td>0 (0x0)</td>
     68<td>S_LOAD_DWORD</td>
     69<td>S_LOAD_DWORD</td>
     70</tr>
     71<tr>
     72<td>1 (0x1)</td>
     73<td>S_LOAD_DWORDX2</td>
     74<td>S_LOAD_DWORDX2</td>
     75</tr>
     76<tr>
     77<td>2 (0x2)</td>
     78<td>S_LOAD_DWORDX4</td>
     79<td>S_LOAD_DWORDX4</td>
     80</tr>
     81<tr>
     82<td>3 (0x3)</td>
     83<td>S_LOAD_DWORDX8</td>
     84<td>S_LOAD_DWORDX8</td>
     85</tr>
     86<tr>
     87<td>4 (0x4)</td>
     88<td>S_LOAD_DWORDX16</td>
     89<td>S_LOAD_DWORDX16</td>
     90</tr>
     91<tr>
     92<td>8 (0x8)</td>
     93<td>S_BUFFER_LOAD_DWORD</td>
     94<td>S_BUFFER_LOAD_DWORD</td>
     95</tr>
     96<tr>
     97<td>9 (0x9)</td>
     98<td>S_BUFFER_LOAD_DWORDX2</td>
     99<td>S_BUFFER_LOAD_DWORDX2</td>
     100</tr>
     101<tr>
     102<td>10 (0xa)</td>
     103<td>S_BUFFER_LOAD_DWORDX4</td>
     104<td>S_BUFFER_LOAD_DWORDX4</td>
     105</tr>
     106<tr>
     107<td>11 (0xb)</td>
     108<td>S_BUFFER_LOAD_DWORDX8</td>
     109<td>S_BUFFER_LOAD_DWORDX8</td>
     110</tr>
     111<tr>
     112<td>12 (0xc)</td>
     113<td>S_BUFFER_LOAD_DWORDX16</td>
     114<td>S_BUFFER_LOAD_DWORDX16</td>
     115</tr>
     116<tr>
     117<td>29 (0x1d)</td>
     118<td>--</td>
     119<td>S_DCACHE_INV_VOL</td>
     120</tr>
     121<tr>
     122<td>30 (0x1e)</td>
     123<td>S_MEMTIME</td>
     124<td>S_MEMTIME</td>
     125</tr>
     126<tr>
     127<td>31 (0x1f)</td>
     128<td>S_DCACHE_INV</td>
     129<td>S_DCACHE_INV</td>
     130</tr>
     131</tbody>
     132</table>
     133<h3>Instruction set</h3>
     134<p>Alphabetically sorted instruction list:</p>
     135<h4>S_BUFFER_LOAD_DWORD</h4>
     136<p>Opcode: 8 (0x8)<br />
     137Syntax: S_BUFFER_LOAD_DWORD SDST, SBASE(4), OFFSET<br />
     138Description: Load single dword from read-only memory through constant cache (kcache).
     139SBASE is buffer descriptor.</p>
     140<h4>S_BUFFER_LOAD_DWORDX16</h4>
     141<p>Opcode: 12 (0xc)<br />
     142Syntax: S_BUFFER_LOAD_DWORDX16 SDST(16), SBASE(4), OFFSET<br />
     143Description: Load 16 dwords from read-only memory through constant cache (kcache).
     144SBASE is buffer descriptor.</p>
     145<h4>S_BUFFER_LOAD_DWORDX2</h4>
     146<p>Opcode: 9 (0x9)<br />
     147Syntax: S_BUFFER_LOAD_DWORDX2 SDST(2), SBASE(4), OFFSET<br />
     148Description: Load two dwords from read-only memory through constant cache (kcache).
     149SBASE is buffer descriptor.</p>
     150<h4>S_BUFFER_LOAD_DWORDX4</h4>
     151<p>Opcode: 10 (0xa)<br />
     152Syntax: S_BUFFER_LOAD_DWORDX4 SDST(4), SBASE(4), OFFSET<br />
     153Description: Load four dwords from read-only memory through constant cache (kcache).
     154SBASE is buffer descriptor.</p>
     155<h4>S_BUFFER_LOAD_DWORDX8</h4>
     156<p>Opcode: 11 (0xb)<br />
     157Syntax: S_BUFFER_LOAD_DWORDX8 SDST(8), SBASE(4), OFFSET<br />
     158Description: Load eight dwords from read-only memory through constant cache (kcache).
     159SBASE is buffer descriptor.</p>
     160<h4>S_DCACHE_INV</h4>
     161<p>Opcode: 31 (0x1f)<br />
     162Syntax: S_DCACHE_INV<br />
     163Description: Invalidate entire L1 K cache.</p>
     164<h4>S_LOAD_DWORD</h4>
     165<p>Opcode: 0 (0x0)<br />
     166Syntax: S_LOAD_DWORD SDST, SBASE(2), OFFSET<br />
     167Description: Load single dword from read-only memory through constant cache (kcache).</p>
     168<h4>S_LOAD_DWORDX16</h4>
     169<p>Opcode: 4 (0x4)<br />
     170Syntax: S_LOAD_DWORDX16 SDST(16), SBASE(2), OFFSET<br />
     171Description: Load 16 dwords from read-only memory through constant cache (kcache).</p>
     172<h4>S_LOAD_DWORDX2</h4>
     173<p>Opcode: 1 (0x1)<br />
     174Syntax: S_LOAD_DWORDX2 SDST(2), SBASE(2), OFFSET<br />
     175Description: Load two dwords from read-only memory through constant cache (kcache).</p>
     176<h4>S_LOAD_DWORDX4</h4>
     177<p>Opcode: 2 (0x2)<br />
     178Syntax: S_LOAD_DWORDX4 SDST(4), SBASE(2), OFFSET<br />
     179Description: Load four dwords from read-only memory through constant cache (kcache).</p>
     180<h4>S_LOAD_DWORDX8</h4>
     181<p>Opcode: 3 (0x3)<br />
     182Syntax: S_LOAD_DWORDX8 SDST(8), SBASE(2), OFFSET<br />
     183Description: Load eight dwords from read-only memory through constant cache (kcache).</p>
     184<h4>S_MEMTIME</h4>
     185<p>Opcode: 30 (0x1e)<br />
     186Syntax: S_MEMTIME SDST(2)<br />
     187Description: Store value of 64-bit clock counter to SDST. Before reading result, S_WAITCNT
     188LGKMCNT(0) is required.<br />
     189Operation:<br />
     190<code>SDST = CLOCKCNT</code></p>
     191}}}