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<h2>GCN ISA SMRD instructions</h2>
<p>The basic encoding of the SMRD instructions needs 4 bytes (dword). List of fields:</p>
<table>
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>0-7</td>
<td>OFFSET</td>
<td>Unsigned 8-bit dword offset or SGPR number that holds byte offset</td>
</tr>
<tr>
<td>8</td>
<td>IMM</td>
<td>IMM indicator</td>
</tr>
<tr>
<td>9-14</td>
<td>SBASE</td>
<td>Number of aligned SGPR pair.</td>
</tr>
<tr>
<td>15-21</td>
<td>SDST</td>
<td>Scalar destination operand</td>
</tr>
<tr>
<td>22-26</td>
<td>OPCODE</td>
<td>Operation code</td>
</tr>
<tr>
<td>27-31</td>
<td>ENCODING</td>
<td>Encoding type. Must be 0b11000</td>
</tr>
</tbody>
</table>
<p>Value of the IMM determines meaningful of the OFFSET field:</p>
<ul>
<li>IMM=1 - OFFSET holds a dword offset to SBASE.</li>
<li>IMM=0 - OFFSET holds number of SGPR that holds byte offset to SBASE.</li>
</ul>
<p>For S_LOAD_DWORD<em> instructions, 2 SBASE SGPRs holds an base 48-bit address and a
16-bit size.
For S_BUFFER_LOAD_DWORD</em> instructions, 4 SBASE SGPRs holds a buffer descriptor.
In this case, SBASE must be a multipla of 2.</p>
<p>List of the instructions by opcode:</p>
<table>
<thead>
<tr>
<th>Opcode</th>
<th>Mnemonic (GCN1.0)</th>
<th>Mnemonic (GCN1.0)</th>
</tr>
</thead>
<tbody>
<tr>
<td>0 (0x0)</td>
<td>S_LOAD_DWORD</td>
<td>S_LOAD_DWORD</td>
</tr>
<tr>
<td>1 (0x1)</td>
<td>S_LOAD_DWORDX2</td>
<td>S_LOAD_DWORDX2</td>
</tr>
<tr>
<td>2 (0x2)</td>
<td>S_LOAD_DWORDX4</td>
<td>S_LOAD_DWORDX4</td>
</tr>
<tr>
<td>3 (0x3)</td>
<td>S_LOAD_DWORDX8</td>
<td>S_LOAD_DWORDX8</td>
</tr>
<tr>
<td>4 (0x4)</td>
<td>S_LOAD_DWORDX16</td>
<td>S_LOAD_DWORDX16</td>
</tr>
<tr>
<td>8 (0x8)</td>
<td>S_BUFFER_LOAD_DWORD</td>
<td>S_BUFFER_LOAD_DWORD</td>
</tr>
<tr>
<td>9 (0x9)</td>
<td>S_BUFFER_LOAD_DWORDX2</td>
<td>S_BUFFER_LOAD_DWORDX2</td>
</tr>
<tr>
<td>10 (0xa)</td>
<td>S_BUFFER_LOAD_DWORDX4</td>
<td>S_BUFFER_LOAD_DWORDX4</td>
</tr>
<tr>
<td>11 (0xb)</td>
<td>S_BUFFER_LOAD_DWORDX8</td>
<td>S_BUFFER_LOAD_DWORDX8</td>
</tr>
<tr>
<td>12 (0xc)</td>
<td>S_BUFFER_LOAD_DWORDX16</td>
<td>S_BUFFER_LOAD_DWORDX16</td>
</tr>
<tr>
<td>29 (0x1d)</td>
<td>--</td>
<td>S_DCACHE_INV_VOL</td>
</tr>
<tr>
<td>30 (0x1e)</td>
<td>S_MEMTIME</td>
<td>S_MEMTIME</td>
</tr>
<tr>
<td>31 (0x1f)</td>
<td>S_DCACHE_INV</td>
<td>S_DCACHE_INV</td>
</tr>
</tbody>
</table>
<h3>Instruction set</h3>
<p>Alphabetically sorted instruction list:</p>
<h4>S_BUFFER_LOAD_DWORD</h4>
<p>Opcode: 8 (0x8)<br />
Syntax: S_BUFFER_LOAD_DWORD SDST, SBASE(4), OFFSET<br />
Description: Load single dword from read-only memory through constant cache (kcache).
SBASE is buffer descriptor.</p>
<h4>S_BUFFER_LOAD_DWORDX16</h4>
<p>Opcode: 12 (0xc)<br />
Syntax: S_BUFFER_LOAD_DWORDX16 SDST(16), SBASE(4), OFFSET<br />
Description: Load 16 dwords from read-only memory through constant cache (kcache).
SBASE is buffer descriptor.</p>
<h4>S_BUFFER_LOAD_DWORDX2</h4>
<p>Opcode: 9 (0x9)<br />
Syntax: S_BUFFER_LOAD_DWORDX2 SDST(2), SBASE(4), OFFSET<br />
Description: Load two dwords from read-only memory through constant cache (kcache).
SBASE is buffer descriptor.</p>
<h4>S_BUFFER_LOAD_DWORDX4</h4>
<p>Opcode: 10 (0xa)<br />
Syntax: S_BUFFER_LOAD_DWORDX4 SDST(4), SBASE(4), OFFSET<br />
Description: Load four dwords from read-only memory through constant cache (kcache).
SBASE is buffer descriptor.</p>
<h4>S_BUFFER_LOAD_DWORDX8</h4>
<p>Opcode: 11 (0xb)<br />
Syntax: S_BUFFER_LOAD_DWORDX8 SDST(8), SBASE(4), OFFSET<br />
Description: Load eight dwords from read-only memory through constant cache (kcache).
SBASE is buffer descriptor.</p>
<h4>S_DCACHE_INV</h4>
<p>Opcode: 31 (0x1f)<br />
Syntax: S_DCACHE_INV<br />
Description: Invalidate entire L1 K cache.</p>
<h4>S_LOAD_DWORD</h4>
<p>Opcode: 0 (0x0)<br />
Syntax: S_LOAD_DWORD SDST, SBASE(2), OFFSET<br />
Description: Load single dword from read-only memory through constant cache (kcache).</p>
<h4>S_LOAD_DWORDX16</h4>
<p>Opcode: 4 (0x4)<br />
Syntax: S_LOAD_DWORDX16 SDST(16), SBASE(2), OFFSET<br />
Description: Load 16 dwords from read-only memory through constant cache (kcache).</p>
<h4>S_LOAD_DWORDX2</h4>
<p>Opcode: 1 (0x1)<br />
Syntax: S_LOAD_DWORDX2 SDST(2), SBASE(2), OFFSET<br />
Description: Load two dwords from read-only memory through constant cache (kcache).</p>
<h4>S_LOAD_DWORDX4</h4>
<p>Opcode: 2 (0x2)<br />
Syntax: S_LOAD_DWORDX4 SDST(4), SBASE(2), OFFSET<br />
Description: Load four dwords from read-only memory through constant cache (kcache).</p>
<h4>S_LOAD_DWORDX8</h4>
<p>Opcode: 3 (0x3)<br />
Syntax: S_LOAD_DWORDX8 SDST(8), SBASE(2), OFFSET<br />
Description: Load eight dwords from read-only memory through constant cache (kcache).</p>
<h4>S_MEMTIME</h4>
<p>Opcode: 30 (0x1e)<br />
Syntax: S_MEMTIME SDST(2)<br />
Description: Store value of 64-bit clock counter to SDST. Before reading result, S_WAITCNT
LGKMCNT(0) is required.<br />
Operation:<br />
<code>SDST = CLOCKCNT</code></p>
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