Changes between Version 2 and Version 3 of GcnInstrsSop2
- Timestamp:
- 11/13/15 09:00:16 (8 years ago)
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GcnInstrsSop2
v2 v3 144 144 <p><code>SDST = SSRC0 + SSRC1 145 145 temp = (UINT64)SSRC0 + (UINT64)SSRC1 146 SCC = temp >((1LL<<31)-1) || temp>(-1LL<<31)</code></p>146 SCC = temp > ((1LL<<31)-1) || temp > (-1LL<<31)</code></p> 147 147 <h4>S_ADD_U32</h4> 148 148 <p>Opcode: 0 (0x0)<br /> … … 159 159 Operation: 160 160 <code>SDST = SSRC0 & SSRC1 161 SCC = (SSRC0 & SSRC1)!=0</code></p>161 SCC = SDST!=0</code></p> 162 162 <h4>S_AND_B64</h4> 163 163 <p>Opcode: 15 (0xf)<br /> 164 164 Syntax: S_AND_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 165 165 Description: Do bitwise AND operation on SSRC0 and SSRC1 and store it to SDST, and store 166 1 to SCC if result is not zero, otherwise store 0 to SCC. <br />166 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 167 167 Operation: 168 168 <code>SDST = SSRC0 & SSRC1 169 SCC = (SSRC0 & SSRC1)!=0</code></p>169 SCC = SDST!=0</code></p> 170 170 <h4>S_ANDN2_B32</h4> 171 171 <p>Opcode: 20 (0x14)<br /> … … 175 175 Operation: 176 176 <code>SDST = SSRC0 & ~SSRC1 177 SCC = (SSRC0 & ~SSRC1)!=0</code></p>177 SCC = SDST!=0</code></p> 178 178 <h4>S_ANDN2_B64</h4> 179 179 <p>Opcode: 21 (0x15)<br /> 180 180 Syntax: S_ANDN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 181 181 Description: Do bitwise AND operation on SSRC0 and bitwise negated SSRC1 and store 182 it to SDST, and store 1 to SCC if result is not zero, otherwise store 0 to SCC.<br /> 182 it to SDST, and store 1 to SCC if result is not zero, otherwise store 0 to SCC. 183 SDST, SSRC0, SSRC1 are 64-bit.<br /> 183 184 Operation: 184 185 <code>SDST = SSRC0 & ~SSRC1 185 SCC = (SSRC0 & ~SSRC1)!=0</code></p>186 SCC = SDST!=0</code></p> 186 187 <h4>S_CSELECT_B32</h4> 187 188 <p>Opcode: 10 (0xa)<br /> … … 198 199 Operation: 199 200 <code>SDST = SCC ? SSRC0 : SSRC1</code></p> 201 <h4>S_LSHL_B32</h4> 202 <p>Opcode: 30 (0x1e) 203 Syntax: S_LSHL_B32 SDST, SSRC0, SSRC1<br /> 204 Description: Shift to left SSRC0 by (SSRC1&31) bits and store result into SDST. 205 If result is non-zero store 1 to SCC, otherwise store 0 to SCC.<br /> 206 Operation:<br /> 207 <code>SDST = (SSRC0) << (SSRC1 & 31) 208 SCC = SDST!=0</code></p> 209 <h4>S_LSHL_B64</h4> 210 <p>Opcode: 31 (0x1f) 211 Syntax: S_LSHL_B64 SDST(2), SSRC0(2), SSRC1<br /> 212 Description: Shift to left SSRC0 by (SSRC1&31) bits and store result into SDST. 213 If result is non-zero store 1 to SCC, otherwise store 0 to SCC. SDST, SSRC0 are 64-bit, 214 SSRC1 is 32 bit.<br /> 215 Operation:<br /> 216 <code>SDST = (SSRC0) << (SSRC1 & 63) 217 SCC = SDST!=0</code></p> 200 218 <h4>S_MIN_I32</h4> 201 219 <p>Opcode: 6 (0x6) … … 204 222 and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br /> 205 223 Operation:<br /> 206 <code>SDST = (INT32)SSSRC0 <(INT32)SSSRC1 ? SSSRC0 : SSSRC1207 SCC = (INT32)SSSRC0 <(INT32)SSSRC1</code></p>224 <code>SDST = (INT32)SSSRC0 < (INT32)SSSRC1 ? SSSRC0 : SSSRC1 225 SCC = (INT32)SSSRC0 < (INT32)SSSRC1</code></p> 208 226 <h4>S_MIN_U32</h4> 209 227 <p>Opcode: 7 (0x7)<br /> … … 212 230 and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br /> 213 231 Operation:<br /> 214 <code>SDST = (UINT32)SSSRC0 <(UINT32)SSSRC1 ? SSSRC0 : SSSRC1215 SCC = (UINT32)SSSRC0 <(UINT32)SSSRC1</code></p>232 <code>SDST = (UINT32)SSSRC0 < (UINT32)SSSRC1 ? SSSRC0 : SSSRC1 233 SCC = (UINT32)SSSRC0 < (UINT32)SSSRC1</code></p> 216 234 <h4>S_MAX_I32</h4> 217 235 <p>Opcode: 8 (0x9) … … 220 238 and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br /> 221 239 Operation:<br /> 222 <code>SDST = (INT32)SSSRC0 >(INT32)SSSRC1 ? SSSRC0 : SSSRC1223 SCC = (INT32)SSSRC0 >(INT32)SSSRC1</code></p>240 <code>SDST = (INT32)SSSRC0 > (INT32)SSSRC1 ? SSSRC0 : SSSRC1 241 SCC = (INT32)SSSRC0 > (INT32)SSSRC1</code></p> 224 242 <h4>S_MAX_U32</h4> 225 243 <p>Opcode: 9 (0x9)<br /> … … 228 246 and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br /> 229 247 Operation:<br /> 230 <code>SDST = (UINT32)SSSRC0>(UINT32)SSSRC1 ? SSSRC0 : SSSRC1 231 SCC = (UINT32)SSSRC0>(UINT32)SSSRC1</code></p> 248 <code>SDST = (UINT32)SSSRC0 > (UINT32)SSSRC1 ? SSSRC0 : SSSRC1 249 SCC = (UINT32)SSSRC0 > (UINT32)SSSRC1</code></p> 250 <h4>S_NAND_B32</h4> 251 <p>Opcode: 24 (0x18)<br /> 252 Syntax: S_NAND_B32 SDST, SSRC0, SSRC1<br /> 253 Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store 254 1 to SCC if result is not zero, otherwise store 0 to SCC.<br /> 255 Operation: 256 <code>SDST = ~(SSRC0 & SSRC1) 257 SCC = SDST!=0</code></p> 258 <h4>S_NAND_B64</h4> 259 <p>Opcode: 25 (0x19)<br /> 260 Syntax: S_NAND_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 261 Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store 262 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 263 Operation: 264 <code>SDST = ~(SSRC0 & SSRC1) 265 SCC = SDST!=0</code></p> 266 <h4>S_NOR_B32</h4> 267 <p>Opcode: 26 (0x1a)<br /> 268 Syntax: S_NOR_B32 SDST, SSRC0, SSRC1<br /> 269 Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store 270 1 to SCC if result is not zero, otherwise store 0 to SCC.<br /> 271 Operation: 272 <code>SDST = ~(SSRC0 | SSRC1) 273 SCC = SDST!=0</code></p> 274 <h4>S_NOR_B64</h4> 275 <p>Opcode: 27 (0x1b)<br /> 276 Syntax: S_NOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 277 Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store 278 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 279 Operation: 280 <code>SDST = ~(SSRC0 | SSRC1) 281 SCC = SDST!=0</code></p> 232 282 <h4>S_OR_B32</h4> 233 283 <p>Opcode: 16 (0x10)<br /> … … 237 287 Operation: 238 288 <code>SDST = SSRC0 | SSRC1 239 SCC = (SSRC0 | SSRC1)!=0</code></p>289 SCC = SDST!=0</code></p> 240 290 <h4>S_OR_B64</h4> 241 291 <p>Opcode: 17 (0x11)<br /> 242 292 Syntax: S_OR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 243 293 Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store 244 1 to SCC if result is not zero, otherwise store 0 to SCC. <br />294 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 245 295 Operation: 246 296 <code>SDST = SSRC0 | SSRC1 247 SCC = (SSRC0 | SSRC1)!=0</code></p>297 SCC = SDST!=0</code></p> 248 298 <h4>S_ORN2_B32</h4> 249 299 <p>Opcode: 22 (0x16)<br /> … … 253 303 Operation: 254 304 <code>SDST = SSRC0 | ~SSRC1 255 SCC = (SSRC0 | ~SSRC1)!=0</code></p>305 SCC = SDST!=0</code></p> 256 306 <h4>S_ORN2_B64</h4> 257 307 <p>Opcode: 23 (0x17)<br /> 258 308 Syntax: S_ORN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 259 309 Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST, 260 and store 1 to SCC if result is not zero, otherwise store 0 to SCC.<br /> 310 and store 1 to SCC if result is not zero, otherwise store 0 to SCC. 311 SDST, SSRC0, SSRC1 are 64-bit.<br /> 261 312 Operation: 262 313 <code>SDST = SSRC0 | ~SSRC1 263 SCC = (SSRC0 | ~SSRC1)!=0</code></p>314 SCC = SDST!=0</code></p> 264 315 <h4>S_SUBB_U32</h4> 265 316 <p>Opcode: 5 (0x5)<br /> … … 288 339 <code>SDST = SSRC0 - SSRC1 289 340 SCC = ((INT64)SSRC0 - (INT64)SSRC1)>>32</code></p> 341 <h4>S_XNOR_B32</h4> 342 <p>Opcode: 28 (0x1c)<br /> 343 Syntax: S_XNOR_B32 SDST, SSRC0, SSRC1<br /> 344 Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store 345 1 to SCC if result is not zero, otherwise store 0 to SCC.<br /> 346 Operation: 347 <code>SDST = ~(SSRC0 ^ SSRC1) 348 SCC = SDST!=0</code></p> 349 <h4>S_XNOR_B64</h4> 350 <p>Opcode: 29 (0x1d)<br /> 351 Syntax: S_XNOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 352 Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store 353 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 354 Operation: 355 <code>SDST = ~(SSRC0 ^ SSRC1) 356 SCC = SDST!=0</code></p> 290 357 <h4>S_XOR_B32</h4> 291 358 <p>Opcode: 18 (0x12)<br /> … … 295 362 Operation:<br /> 296 363 <code>SDST = SSRC0 ^ SSRC1 297 SCC = (SSRC0 ^ SSRC1)!=0</code></p>364 SCC = SDST!=0</code></p> 298 365 <h4>S_XOR_B64</h4> 299 366 <p>Opcode: 19 (0x13)<br /> 300 367 Syntax: S_XOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 301 368 Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store 302 1 to SCC if result is not zero, otherwise store 0 to SCC. <br />369 1 to SCC if result is not zero, otherwise store 0 to SCC. SDST, SSRC0, SSRC1 are 64-bit.<br /> 303 370 Operation:<br /> 304 371 <code>SDST = SSRC0 ^ SSRC1 305 SCC = (SSRC0 ^ SSRC1)!=0</code></p>372 SCC = SDST!=0</code></p> 306 373 }}}