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<h2>GCN ISA SOP2 instructions</h2>
<h3>Encoding</h3>
<p>The basic encoding of the SOP2 instructions needs 4 bytes (dword). List of fields:</p>
<table>
<thead>
<tr>
<th>Bits</th>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>0-7</td>
<td>SSRC0</td>
<td>First scalar source operand. Refer to operand encoding</td>
</tr>
<tr>
<td>8-15</td>
<td>SSRC1</td>
<td>Second scalar source operand. Refer to operand encoding</td>
</tr>
<tr>
<td>16-22</td>
<td>SDST</td>
<td>Destination scalar operand. Refer to operand encoding</td>
</tr>
<tr>
<td>23-29</td>
<td>OPCODE</td>
<td>Operation code</td>
</tr>
<tr>
<td>30-31</td>
<td>ENCODING</td>
<td>Encoding type. Must be 0b10</td>
</tr>
</tbody>
</table>
<p>Syntax for all instructions: INSTRUCTION SDST, SSRC0, SSRC1</p>
<p>Example: s_and_b32 s0, s1, s2</p>
<p>List of the instruction by opcode:</p>
<table>
<thead>
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
</tr>
</thead>
<tbody>
<tr>
<td>0</td>
<td>S_ADD_U32</td>
</tr>
<tr>
<td>1</td>
<td>S_SUB_U32</td>
</tr>
<tr>
<td>2</td>
<td>S_ADD_I32</td>
</tr>
<tr>
<td>3</td>
<td>S_SUB_I32</td>
</tr>
<tr>
<td>4</td>
<td>S_ADDC_U32</td>
</tr>
<tr>
<td>5</td>
<td>S_SUBB_U32</td>
</tr>
<tr>
<td>6</td>
<td>S_MIN_I32</td>
</tr>
<tr>
<td>7</td>
<td>S_MIN_U32</td>
</tr>
</tbody>
</table>
<h3>Instruction set</h3>
<p>Alphabetically sorted instruction list:</p>
<h4>S_ADDC_U32</h4>
<p>Opcode: 4 (0x4)<br />
Syntax: S_ADDC_U32 SDST, SSRC0, SSRC1<br />
Descrition: Add SSRC0 to SSRC1 with SCC value and store result into SDST and store
carry-out flag into SCC.<br />
Operation:<br />
<code>temp = (UINT64)SSRC0 + (UINT64)SSRC1 + SCC
SDST = temp
SCC = temp&gt;&gt;32</code></p>
<h4>S_ADD_I32</h4>
<p>Opcode: 2 (0x2)<br />
Syntax: S_ADD_I32 SDST, SSRC0, SSRC1<br />
Description: Add SSRC0 to SSRC1 and store result into SDST and store overflow flag into SCC.<br />
Operation:  </p>
<p><code>SDST = SSRC0 + SSRC1
temp = (UINT64)SSRC0 + (UINT64)SSRC1
SCC = temp&gt;((1LL&lt;&lt;31)-1) || temp&gt;(-1LL&lt;&lt;31)</code></p>
<h4>S_ADD_U32</h4>
<p>Opcode: 0 (0x0)<br />
Syntax: S_ADD_U32 SDST, SSRC0, SSRC1<br />
Description: Add SSRC0 to SSRC1 and store result into SDST and store carry-out into SCC.<br />
Operation:<br />
<code>SDST = SSRC0 + SSRC1
SCC = ((UINT64)SSRC0 + (UINT64)SSRC1)&gt;&gt;32</code></p>
<h4>S_MIN_I32</h4>
<p>Opcode: 6 (0x6)
Syntax: S_MIN_I32 SDST, SSRC0, SSRC1<br />
Description: Choose smallest signed value value from SSRC0 and SSRC1 and store its into SDST,
and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br />
Operation:<br />
<code>SDST = (INT32)SSSRC0&lt;(INT32)SSSRC1 ? SSSRC0 : SSSRC1
SCC = (INT32)SSSRC0&lt;(INT32)SSSRC1</code></p>
<h4>S_MIN_U32</h4>
<p>Opcode: 7 (0x7)<br />
Syntax: S_MIN_U32 SDST, SSRC0, SSRC1<br />
Description: Choose smallest unsigned value value from SSRC0 and SSRC1 and store its into SDST,
and store 1 to SCC if SSSRC0 value has been choosen, otherwise store 0 to SCC<br />
Operation:<br />
<code>SDST = (UINT32)SSSRC0&lt;(UINT32)SSSRC1 ? SSSRC0 : SSSRC1
SCC = (UINT32)SSSRC0&lt;(UINT32)SSSRC1</code></p>
<h4>S_SUBB_U32</h4>
<p>Opcode: 5 (0x5)<br />
Syntax: S_SUBB_U32 SDST, SSRC0, SSRC1<br />
Descrition: Subtract SSRC0 to SSRC1 with SCC value and store result into SDST and store
carry-out flag into SCC.<br />
Operation:<br />
<code>temp = (UINT64)SSRC0 - (UINT64)SSRC1 - SCC
SDST = temp
SCC = temp&gt;&gt;32</code></p>
<h4>S_SUB_I32</h4>
<p>Opcode: 3 (0x3)<br />
Syntax: S_SUB_I32 SDST, SSRC0, SSRC1<br />
Description: Subtract SSRC0 to SSRC1 and store result into SDST and
store overflow flag into SCC. SCC register value can be BROKEN for some
architectures (GCN1.0)<br />
Operation:<br />
<code>SDST = SSRC0 - SSRC1
temp = (UINT64)SSRC0 - (UINT64)SSRC1
SCC = temp&gt;((1LL&lt;&lt;31)-1) || temp&gt;(-1LL&lt;&lt;31)</code></p>
<h4>S_SUB_U32</h4>
<p>Opcode: 1 (0x1)<br />
Syntax: S_SUB_U32 SDST, SSRC0, SSRC1<br />
Description: Subtract SSRC0 to SSRC1 and store result into SDST and store borrow into SCC.<br />
Operation:<br />
<code>SDST = SSRC0 - SSRC1
SCC = ((INT64)SSRC0 - (INT64)SSRC1)&gt;&gt;32</code></p>
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