Changes between Initial Version and Version 1 of GcnInstrsSopk


Ignore:
Timestamp:
11/14/15 18:00:33 (8 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • GcnInstrsSopk

    v1 v1  
     1[wiki:ClrxToc Back to Table of content]
     2{{{
     3#!html
     4<h2>GCN ISA SOPK instructions</h2>
     5<p>The basic encoding of the SOP2 instructions needs 4 bytes (dword). List of fields:</p>
     6<table>
     7<thead>
     8<tr>
     9<th>Bits</th>
     10<th>Name</th>
     11<th>Description</th>
     12</tr>
     13</thead>
     14<tbody>
     15<tr>
     16<td>0-15</td>
     17<td>SIMM16</td>
     18<td>Signed 16-bit immediate value</td>
     19</tr>
     20<tr>
     21<td>16-22</td>
     22<td>SDST</td>
     23<td>Destination scalar operand. Refer to operand encoding</td>
     24</tr>
     25<tr>
     26<td>23-27</td>
     27<td>OPCODE</td>
     28<td>Operation code</td>
     29</tr>
     30<tr>
     31<td>28-31</td>
     32<td>ENCODING</td>
     33<td>Encoding type. Must be 0b1011</td>
     34</tr>
     35</tbody>
     36</table>
     37<p>Syntax for almost instructions: INSTRUCTION SDST, SIMM16</p>
     38<p>SIMM16 - signed 16-bit immediate. IMM16 - unsigned 16-bit immediate.</p>
     39<p>List of the instructions by opcode:</p>
     40<table>
     41<thead>
     42<tr>
     43<th>Opcode</th>
     44<th>Mnemonic (GCN1.0/1.1)</th>
     45<th>Mnemonic (GCN 1.2)</th>
     46</tr>
     47</thead>
     48<tbody>
     49<tr>
     50<td>0 (0x0)</td>
     51<td>S_MOVK_I32</td>
     52<td>S_MOVK_I32</td>
     53</tr>
     54<tr>
     55<td>1 (0x1)</td>
     56<td>--</td>
     57<td>S_CMOVK_I32</td>
     58</tr>
     59<tr>
     60<td>2 (0x2)</td>
     61<td>S_CMOVK_I32</td>
     62<td>S_CMPK_EQ_I32</td>
     63</tr>
     64<tr>
     65<td>3 (0x3)</td>
     66<td>S_CMPK_EQ_I32</td>
     67<td>S_CMPK_LG_I32</td>
     68</tr>
     69<tr>
     70<td>4 (0x4)</td>
     71<td>S_CMPK_LG_I32</td>
     72<td>S_CMPK_GT_I32</td>
     73</tr>
     74<tr>
     75<td>5 (0x5)</td>
     76<td>S_CMPK_GT_I32</td>
     77<td>S_CMPK_GE_I32</td>
     78</tr>
     79<tr>
     80<td>6 (0x6)</td>
     81<td>S_CMPK_GE_I32</td>
     82<td>S_CMPK_LT_I32</td>
     83</tr>
     84<tr>
     85<td>7 (0x7)</td>
     86<td>S_CMPK_LT_I32</td>
     87<td>S_CMPK_LE_I32</td>
     88</tr>
     89<tr>
     90<td>8 (0x8)</td>
     91<td>S_CMPK_LE_I32</td>
     92<td>S_CMPK_EQ_U32</td>
     93</tr>
     94<tr>
     95<td>9 (0x9)</td>
     96<td>S_CMPK_EQ_U32</td>
     97<td>S_CMPK_LG_U32</td>
     98</tr>
     99<tr>
     100<td>10 (0xa)</td>
     101<td>S_CMPK_LG_U32</td>
     102<td>S_CMPK_GT_U32</td>
     103</tr>
     104<tr>
     105<td>11 (0xb)</td>
     106<td>S_CMPK_GT_U32</td>
     107<td>S_CMPK_GE_U32</td>
     108</tr>
     109<tr>
     110<td>12 (0xc)</td>
     111<td>S_CMPK_GE_U32</td>
     112<td>S_CMPK_LT_U32</td>
     113</tr>
     114<tr>
     115<td>13 (0xd)</td>
     116<td>S_CMPK_LT_U32</td>
     117<td>S_CMPK_LE_U32</td>
     118</tr>
     119<tr>
     120<td>14 (0xe)</td>
     121<td>S_CMPK_LE_U32</td>
     122<td>S_ADDK_I32</td>
     123</tr>
     124<tr>
     125<td>15 (0xf)</td>
     126<td>S_ADDK_I32</td>
     127<td>S_MULK_I32</td>
     128</tr>
     129<tr>
     130<td>16 (0x10)</td>
     131<td>S_MULK_I32</td>
     132<td>S_CBRANCH_I_FORK</td>
     133</tr>
     134<tr>
     135<td>17 (0x11)</td>
     136<td>S_CBRANCH_I_FORK</td>
     137<td>S_GETREG_B32</td>
     138</tr>
     139<tr>
     140<td>18 (0x12)</td>
     141<td>S_GETREG_B32</td>
     142<td>S_SETREG_B32</td>
     143</tr>
     144<tr>
     145<td>19 (0x13)</td>
     146<td>S_SETREG_B32</td>
     147<td>S_GETREG_REGRD_B32</td>
     148</tr>
     149<tr>
     150<td>20 (0x14)</td>
     151<td>S_GETREG_REGRD_B32</td>
     152<td>S_SETREG_IMM32_B32</td>
     153</tr>
     154<tr>
     155<td>21 (0x15)</td>
     156<td>S_SETREG_IMM32_B32</td>
     157<td>--</td>
     158</tr>
     159</tbody>
     160</table>
     161<h3>Instruction set</h3>
     162<p>Alphabetically sorted instruction list:</p>
     163<h4>S_ADDK_I32</h4>
     164<p>Opcode: 15 (0xf) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
     165Syntax: S_ADDK_I32 SDST, SIMM16<br />
     166Description: Add signed SDST to SIMM16 and store result into SDST and
     167store overflow flag into SCC.<br />
     168Operation:<br />
     169<code>SDST = SDST + SIMM16
     170INT64 temp = SEXT64(SDST) + SEXT64(SIMM16)
     171SCC = temp &gt; ((1LL&lt;&lt;31)-1) || temp &lt; (-1LL&lt;&lt;31)</code></p>
     172<h4>S_CMOVK_I32</h4>
     173<p>Opcode: 2 (0x2) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2<br />
     174Syntax: S_MOVK_I32 SDST, SIMM16<br />
     175Description: If SCC is 1 then move signed extended 16-bit immediate into SDST.
     176SCC has not been changed.<br />
     177Operation:<br />
     178<code>SDST = SCC ? SIMM16 : SDST</code></p>
     179<h4>S_CMPK_EQ_I32</h4>
     180<p>Opcode: 3 (0x3) for GCN1.0/1.1; 2 (0x2) for GCN 1.2<br />
     181Syntax: S_CMPK_EQ_I32 SDST, SIMM16<br />
     182Description: Compare signed value from SDST with SIMM16. If SDST equal, store 1 to SCC,
     183otherwise store 0 to SCC.<br />
     184Operation:<br />
     185<code>SCC = (INT32)SDST == SIMM16</code></p>
     186<h4>S_CMPK_EQ_U32</h4>
     187<p>Opcode: 9 (0x9) for GCN1.0/1.1; 8 (0x8) for GCN 1.2<br />
     188Syntax: S_CMPK_EQ_U32 SDST, IMM16<br />
     189Description: Compare unsigned value from SDST with IMM16. If SDST equal, store 1 to SCC,
     190otherwise store 0 to SCC.<br />
     191Operation:<br />
     192<code>SCC = SDST == IMM16</code></p>
     193<h4>S_CMPK_GE_I32</h4>
     194<p>Opcode: 6 (0x6) for GCN1.0/1.1; 5 (0x5) for GCN 1.2<br />
     195Syntax: S_CMPK_GE_I32 SDST, SIMM16<br />
     196Description: Compare signed value from SDST with SIMM16. If SDST greater or equal,
     197store 1 to SCC, otherwise store 0 to SCC.<br />
     198Operation:<br />
     199<code>SCC = (INT32)SDST &gt;= SIMM16</code></p>
     200<h4>S_CMPK_GE_U32</h4>
     201<p>Opcode: 12 (0xc) for GCN1.0/1.1; 11 (0xb) for GCN 1.2<br />
     202Syntax: S_CMPK_GE_U32 SDST, IMM16<br />
     203Description: Compare unsigned value from SDST with IMM16. If SDST greater or equal,
     204store 1 to SCC, otherwise store 0 to SCC.<br />
     205Operation:<br />
     206<code>SCC = SDST &gt;= IMM16</code></p>
     207<h4>S_CMPK_GT_I32</h4>
     208<p>Opcode: 5 (0x5) for GCN1.0/1.1; 4 (0x4) for GCN 1.2<br />
     209Syntax: S_CMPK_GT_I32 SDST, SIMM16<br />
     210Description: Compare signed value from SDST with SIMM16. If SDST greater, store 1 to SCC,
     211otherwise store 0 to SCC.<br />
     212Operation:<br />
     213<code>SCC = (INT32)SDST &gt; SIMM16</code></p>
     214<h4>S_CMPK_GT_U32</h4>
     215<p>Opcode: 11 (0xb) for GCN1.0/1.1; 10 (0xa) for GCN 1.2<br />
     216Syntax: S_CMPK_GT_U32 SDST, IMM16<br />
     217Description: Compare unsigned value from SDST with IMM16. If SDST greater, store 1 to SCC,
     218otherwise store 0 to SCC.<br />
     219Operation:<br />
     220<code>SCC = SDST &gt; IMM16</code></p>
     221<h4>S_CMPK_LE_I32</h4>
     222<p>Opcode: 8 (0x8) for GCN1.0/1.1; 7 (0x7) for GCN 1.2<br />
     223Syntax: S_CMPK_LE_I32 SDST, SIMM16<br />
     224Description: Compare signed value from SDST with SIMM16. If SDST less or equal,
     225store 1 to SCC, otherwise store 0 to SCC.<br />
     226Operation:<br />
     227<code>SCC = (INT32)SDST &lt;= SIMM16</code></p>
     228<h4>S_CMPK_LE_U32</h4>
     229<p>Opcode: 14 (0xe) for GCN1.0/1.1; 13 (0xd) for GCN 1.2<br />
     230Syntax: S_CMPK_LE_U32 SDST, IMM16<br />
     231Description: Compare unsigned value from SDST with IMM16. If SDST less or equal,
     232store 1 to SCC, otherwise store 0 to SCC.<br />
     233Operation:<br />
     234<code>SCC = SDST &lt;= IMM16</code></p>
     235<h4>S_CMPK_LG_I32</h4>
     236<p>Opcode: 4 (0x4) for GCN1.0/1.1; 3 (0x3) for GCN 1.2<br />
     237Syntax: S_CMPK_LG_I32 SDST, SIMM16<br />
     238Description: Compare signed value from SDST with SIMM16. If SDST not equal, store 1 to SCC,
     239otherwise store 0 to SCC.<br />
     240Operation:<br />
     241<code>SCC = (INT32)SDST != SIMM16</code></p>
     242<h4>S_CMPK_LG_U32</h4>
     243<p>Opcode: 10 (0xa) for GCN1.0/1.1; 9 (0x9) for GCN 1.2<br />
     244Syntax: S_CMPK_LG_U32 SDST, IMM16<br />
     245Description: Compare unsigned value from SDST with IMM16. If SDST not equal, store 1 to SCC,
     246otherwise store 0 to SCC.<br />
     247Operation:<br />
     248<code>SCC = SDST != IMM16</code></p>
     249<h4>S_CMPK_LT_I32</h4>
     250<p>Opcode: 7 (0x7) for GCN1.0/1.1; 6 (0x6) for GCN 1.2<br />
     251Syntax: S_CMPK_LT_I32 SDST, SIMM16<br />
     252Description: Compare signed value from SDST with SIMM16. If SDST less, store 1 to SCC,
     253otherwise store 0 to SCC.<br />
     254Operation:<br />
     255<code>SCC = (INT32)SDST &lt; SIMM16</code></p>
     256<h4>S_CMPK_LT_U32</h4>
     257<p>Opcode: 13 (0xd) for GCN1.0/1.1; 12 (0xc) for GCN 1.2<br />
     258Syntax: S_CMPK_LT_U32 SDST, IMM16<br />
     259Description: Compare unsigned value from SDST with IMM16. If SDST less, store 1 to SCC,
     260otherwise store 0 to SCC.<br />
     261Operation:<br />
     262<code>SCC = SDST &lt; IMM16</code></p>
     263<h4>S_MOVK_I32</h4>
     264<p>Opcode: 0 (0x0)<br />
     265Syntax: S_MOVK_I32 SDST, SIMM16<br />
     266Description: Move signed extended 16-bit immediate into SDST. SCC has not been changed.<br />
     267Operation:<br />
     268<code>SCC = SIMM16</code></p>
     269<h4>S_MUL_I32</h4>
     270<p>Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
     271Syntax: S_MULK_I32 SDST, SIMM16<br />
     272Description: Multiply signed SDST with SIMM16 and store result into SDST.
     273SCC has not been changed.<br />
     274<code>SDST = SDST * SIMM16</code></p>
     275}}}