Changes between Version 2 and Version 3 of GcnInstrsSopk


Ignore:
Timestamp:
Nov 14, 2015, 11:00:34 PM (5 years ago)
Author:
trac
Comment:

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  • GcnInstrsSopk

    v2 v3  
    293293Operation:<br />
    294294<code>SCC = SDST &lt; IMM16</code></p>
     295<h4>S_GETREG_B32</h4>
     296<p>Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2<br />
     297Syntax: S_GETREG_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE)<br />
     298Description: Store hardware register part to SDST. BITOFFSET (0-31) is first bit in
     299hardware register, BITSIZE (1-32) is number of bits to extract.<br />
     300Operation:<br />
     301<code>SDST = (HWREG &gt;&gt; BITOFFSET) &amp; ((1U &lt;&lt; BITSIZE) - 1U)</code></p>
    295302<h4>S_MOVK_I32</h4>
    296303<p>Opcode: 0 (0x0)<br />
     
    305312SCC has not been changed.<br />
    306313<code>SDST = SDST * SIMM16</code></p>
     314<h4>S_SETREG_B32</h4>
     315<p>Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2<br />
     316Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), SDST<br />
     317Description: Store value from SDST to part of the hardware register.
     318BITOFFSET (0-31) is first bit in hardware register,
     319BITSIZE (1-32) is number of bits to store.<br />
     320Operation:<br />
     321<code>UINT32 mask = ((1U&lt;&lt;BITSIZE) - 1U) &lt;&lt; BITOFFSET
     322HWREG = (HWREG &amp; ~mask) | ((SDST&lt;&lt;BITOFFSET) &amp; mask)</code></p>
     323<h4>S_SETREG_IMM32_B32</h4>
     324<p>Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2<br />
     325Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), IMM32<br />
     326Description: Store value from IMM32 to part of the hardware register.
     327BITOFFSET (0-31) is first bit in hardware register,
     328BITSIZE (1-32) is number of bits to store. IMM32 is immediate 32-bit value after
     329instruction dword.<br />
     330Operation:<br />
     331<code>UINT32 mask = ((1U&lt;&lt;BITSIZE) - 1U) &lt;&lt; BITOFFSET
     332HWREG = (HWREG &amp; ~mask) | ((IMM32&lt;&lt;BITOFFSET) &amp; mask)</code></p>
    307333}}}