Changes between Initial Version and Version 1 of GcnInstrsSopp


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Timestamp:
11/16/15 23:00:23 (8 years ago)
Author:
trac
Comment:

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  • GcnInstrsSopp

    v1 v1  
     1[wiki:ClrxToc Back to Table of content]
     2{{{
     3#!html
     4<h2>GCN ISA SOPP instructions</h2>
     5<p>The basic encoding of the SOPP instructions needs 4 bytes (dword). List of fields:</p>
     6<table>
     7<thead>
     8<tr>
     9<th>Bits</th>
     10<th>Name</th>
     11<th>Description</th>
     12</tr>
     13</thead>
     14<tbody>
     15<tr>
     16<td>0-15</td>
     17<td>SIMM16</td>
     18<td>Signed or unsigned 16-bit immediate value</td>
     19</tr>
     20<tr>
     21<td>16-22</td>
     22<td>OPCODE</td>
     23<td>Operation code</td>
     24</tr>
     25<tr>
     26<td>23-31</td>
     27<td>ENCODING</td>
     28<td>Encoding type. Must be 0b101111110</td>
     29</tr>
     30</tbody>
     31</table>
     32<p>Syntax for almost instructions: INSTRUCTION SDST, SIMM16</p>
     33<p>SIMM16 - signed 16-bit immediate. IMM16 - unsigned 16-bit immediate.<br />
     34RELADDR - relative offset to this instruction (can be label or relative expresion).
     35RELADDR = NEXTPC + SIMM16, NEXTPC - PC for next instruction.</p>
     36<p>List of the instructions by opcode:</p>
     37<table>
     38<thead>
     39<tr>
     40<th>Opcode</th>
     41<th>GCN 1.0</th>
     42<th>GCN 1.1</th>
     43<th>GCN 1.2</th>
     44<th>Mnemonic</th>
     45</tr>
     46</thead>
     47<tbody>
     48<tr>
     49<td>0 (0x0)</td>
     50<td>✓</td>
     51<td>✓</td>
     52<td>✓</td>
     53<td>S_NOP</td>
     54</tr>
     55<tr>
     56<td>1 (0x1)</td>
     57<td>✓</td>
     58<td>✓</td>
     59<td>✓</td>
     60<td>S_ENDPGM</td>
     61</tr>
     62<tr>
     63<td>2 (0x2)</td>
     64<td>✓</td>
     65<td>✓</td>
     66<td>✓</td>
     67<td>S_BRANCH</td>
     68</tr>
     69<tr>
     70<td>3 (0x3)</td>
     71<td></td>
     72<td></td>
     73<td>✓</td>
     74<td>S_WAKEUP</td>
     75</tr>
     76<tr>
     77<td>4 (0x4)</td>
     78<td>✓</td>
     79<td>✓</td>
     80<td>✓</td>
     81<td>S_CBRANCH_SCC0</td>
     82</tr>
     83<tr>
     84<td>5 (0x5)</td>
     85<td>✓</td>
     86<td>✓</td>
     87<td>✓</td>
     88<td>S_CBRANCH_SCC1</td>
     89</tr>
     90<tr>
     91<td>6 (0x6)</td>
     92<td>✓</td>
     93<td>✓</td>
     94<td>✓</td>
     95<td>S_CBRANCH_VCCZ</td>
     96</tr>
     97<tr>
     98<td>7 (0x7)</td>
     99<td>✓</td>
     100<td>✓</td>
     101<td>✓</td>
     102<td>S_CBRANCH_VCCNZ</td>
     103</tr>
     104<tr>
     105<td>8 (0x8)</td>
     106<td>✓</td>
     107<td>✓</td>
     108<td>✓</td>
     109<td>S_CBRANCH_EXECZ</td>
     110</tr>
     111<tr>
     112<td>9 (0x9)</td>
     113<td>✓</td>
     114<td>✓</td>
     115<td>✓</td>
     116<td>S_CBRANCH_EXECNZ</td>
     117</tr>
     118<tr>
     119<td>10 (0xa)</td>
     120<td>✓</td>
     121<td>✓</td>
     122<td>✓</td>
     123<td>S_BARRIER</td>
     124</tr>
     125<tr>
     126<td>11 (0xb)</td>
     127<td></td>
     128<td>✓</td>
     129<td>✓</td>
     130<td>S_SETKILL</td>
     131</tr>
     132<tr>
     133<td>12 (0xc)</td>
     134<td>✓</td>
     135<td>✓</td>
     136<td>✓</td>
     137<td>S_WAITCNT</td>
     138</tr>
     139<tr>
     140<td>13 (0xd)</td>
     141<td>✓</td>
     142<td>✓</td>
     143<td>✓</td>
     144<td>S_SETHALT</td>
     145</tr>
     146<tr>
     147<td>14 (0xe)</td>
     148<td>✓</td>
     149<td>✓</td>
     150<td>✓</td>
     151<td>S_SLEEP</td>
     152</tr>
     153<tr>
     154<td>15 (0xf)</td>
     155<td>✓</td>
     156<td>✓</td>
     157<td>✓</td>
     158<td>S_SETPRIO</td>
     159</tr>
     160<tr>
     161<td>16 (0x10)</td>
     162<td>✓</td>
     163<td>✓</td>
     164<td>✓</td>
     165<td>S_SENDMSG</td>
     166</tr>
     167<tr>
     168<td>17 (0x11)</td>
     169<td>✓</td>
     170<td>✓</td>
     171<td>✓</td>
     172<td>S_SENDMSGHALT</td>
     173</tr>
     174<tr>
     175<td>18 (0x12)</td>
     176<td>✓</td>
     177<td>✓</td>
     178<td>✓</td>
     179<td>S_TRAP</td>
     180</tr>
     181<tr>
     182<td>19 (0x13)</td>
     183<td>✓</td>
     184<td>✓</td>
     185<td>✓</td>
     186<td>S_ICACHE_INV</td>
     187</tr>
     188<tr>
     189<td>20 (0x14)</td>
     190<td>✓</td>
     191<td>✓</td>
     192<td>✓</td>
     193<td>S_INCPERFLEVEL</td>
     194</tr>
     195<tr>
     196<td>21 (0x15)</td>
     197<td>✓</td>
     198<td>✓</td>
     199<td>✓</td>
     200<td>S_DECPERFLEVEL</td>
     201</tr>
     202<tr>
     203<td>22 (0x16)</td>
     204<td>✓</td>
     205<td>✓</td>
     206<td>✓</td>
     207<td>S_TTRACEDATA</td>
     208</tr>
     209<tr>
     210<td>23 (0x17)</td>
     211<td></td>
     212<td>✓</td>
     213<td>✓</td>
     214<td>S_CBRANCH_CDBGSYS</td>
     215</tr>
     216<tr>
     217<td>24 (0x18)</td>
     218<td></td>
     219<td>✓</td>
     220<td>✓</td>
     221<td>S_CBRANCH_CDBGUSER</td>
     222</tr>
     223<tr>
     224<td>25 (0x19)</td>
     225<td></td>
     226<td>✓</td>
     227<td>✓</td>
     228<td>S_CBRANCH_CDBGSYS_OR_USER</td>
     229</tr>
     230<tr>
     231<td>26 (0x1a)</td>
     232<td></td>
     233<td>✓</td>
     234<td>✓</td>
     235<td>S_CBRANCH_CDBGSYS_AND_USER</td>
     236</tr>
     237<tr>
     238<td>27 (0x1b)</td>
     239<td></td>
     240<td></td>
     241<td>✓</td>
     242<td>S_ENDPGM_SAVED</td>
     243</tr>
     244<tr>
     245<td>28 (0x1c)</td>
     246<td></td>
     247<td></td>
     248<td>✓</td>
     249<td>S_SET_GPR_IDX_OFF</td>
     250</tr>
     251<tr>
     252<td>29 (0x1d)</td>
     253<td></td>
     254<td></td>
     255<td>✓</td>
     256<td>S_SET_GPR_IDX_MODE</td>
     257</tr>
     258</tbody>
     259</table>
     260<h3>Instruction set</h3>
     261<p>Alphabetically sorted instruction list:</p>
     262<h4>S_BARRIER</h4>
     263<p>Opcode: 10 (0xa)<br />
     264Syntax: S_BARRIER<br />
     265Description: Synchronize waves within workgroup.</p>
     266<h4>S_BRANCH</h4>
     267<p>Opcode: 2 (0x2)<br />
     268Syntax: S_BRANCH RELADDR<br />
     269Description: Jump to address RELADDR (store RELADDR to PC).<br />
     270Operation:<br />
     271<code>PC = RELADDR</code></p>
     272<h4>S_CBRANCH_EXECNZ</h4>
     273<p>Opcode: 9 (0x9)<br />
     274Syntax: S_CBRANCH_EXECNZ RELADDR<br />
     275Description: If EXEC is not zero then jump to RELADDR, otherwise jump to next instruction.<br />
     276Operation:<br />
     277<code>PC = EXEC!=0 ? RELADDR : PC+4</code></p>
     278<h4>S_CBRANCH_EXECZ</h4>
     279<p>Opcode: 8 (0x8)<br />
     280Syntax: S_CBRANCH_EXECZ RELADDR<br />
     281Description: If EXEC is zero then jump to RELADDR, otherwise jump to next instruction.<br />
     282Operation:<br />
     283<code>PC = EXEC==0 ? RELADDR : PC+4</code></p>
     284<h4>S_CBRANCH_SCC0</h4>
     285<p>Opcode: 4 (0x4)<br />
     286Syntax: S_CBRANCH_SCC0 RELADDR<br />
     287Description: If SCC is zero then jump to RELADDR, otherwise jump to next instruction.<br />
     288Operation:<br />
     289<code>PC = SCC0==0 ? RELADDR : PC+4</code></p>
     290<h4>S_CBRANCH_SCC1</h4>
     291<p>Opcode: 5 (0x5)<br />
     292Syntax: S_CBRANCH_SCC1 RELADDR<br />
     293Description: If SCC is one then jump to RELADDR, otherwise jump to next instruction.<br />
     294Operation:<br />
     295<code>PC = SCC0==1 ? RELADDR : PC+4</code></p>
     296<h4>S_CBRANCH_VCCNZ</h4>
     297<p>Opcode: 7 (0x7)<br />
     298Syntax: S_CBRANCH_VCCNZ RELADDR<br />
     299Description: If VCC is not zero then jump to RELADDR, otherwise jump to next instruction.<br />
     300Operation:<br />
     301<code>PC = VCC!=0 ? RELADDR : PC+4</code></p>
     302<h4>S_CBRANCH_VCCZ</h4>
     303<p>Opcode: 6 (0x6)<br />
     304Syntax: S_CBRANCH_VCCZ RELADDR<br />
     305Description: If VCC is zero then jump to RELADDR, otherwise jump to next instruction.<br />
     306Operation:<br />
     307<code>PC = VCC==0 ? RELADDR : PC+4</code></p>
     308<h4>S_ENDPGM</h4>
     309<p>Opcode: 1 (0x1)<br />
     310Syntax: S_ENDPGM<br />
     311Description: End program.</p>
     312<h4>S_SETHALT</h4>
     313<p>Opcode: 13 (0xd)<br />
     314Syntax: S_SETHALT SIMM16<br />
     315Description: Set HALT bit to value SIMM16&amp;1. 1 - halt, 0 - resume.
     316Halt is ignored while PRIV is 1.<br />
     317Operation:<br />
     318<code>HALT = SIMM16&amp;1</code></p>
     319<h4>S_NOP</h4>
     320<p>Opcode: 0 (0x0)<br />
     321Syntax: S_NOP SIMM16<br />
     322Description: Do nothing by (SIMM16&amp;7) + 1 cycles.<br />
     323Operation: nothing</p>
     324<h4>S_WAITCNT</h4>
     325<p>Opcode: 12 (0xc)<br />
     326Syntax: S_WAITCNT VMCNT(X)|EXPCNT(X)|LGKMCNT(X) [&amp;....]<br />
     327Description: Waits for vector memory operations (VMCNT);
     328LDS, GDS, memory operations (LGKMCNT); export memory-write-data operations (EXPCNT).
     329(SIMM16&amp;15) specifies how many VMCNT operations can be unfinished,
     330value 0xf - no wait for VMCNT operations.
     331(SIMM16&gt;&gt;4)&amp;7 specifies how many EXPCNT operations can be unfinished,
     3320x7 - no wait for EXPCNT operations.
     333(SIMM16&gt;&gt;8)&amp;31 specifies how many LGKMCNT operations can be unfinished,
     3340x1f - no wait for LGKM operations.</p>
     335}}}