Changes between Version 10 and Version 11 of GcnInstrsVop1

Timestamp:

11/29/15 17:00:16 (8 years ago)

Author:

trac

Comment:

--

GcnInstrsVop1

@@ -1072 +1072 @@
 <h3>Instruction set</h3>
 <p>Alphabetically sorted instruction list:</p>
+<h4>V_BFREV_B32</h4>
+<p>Opcode VOP1: 56 (0x38) for GCN 1.0/1.1; 44 (0x2c) for GCN 1.2<br />
+Opcode VOP3A: 440 (0x1b8) for GCN 1.0/1.1; 364 (0x16c) for GCN 1.2<br />
+Syntax: V_BFREV_B32 VDST, SRC0<br />
+Reverse bits in SRC0 and store result to VDST.<br />
+Operation:<br />
+<code>VDST = REVBIT(SRC0)</code></p>
 <h4>V_CEIL_F32</h4>
 <p>Opcode VOP1: 34 (0x22) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
@@ -1287 +1294 @@
 else
     VDST = 0.0</code></p>
+<h4>V_FFBH_U32</h4>
+<p>Opcode VOP1: 57 (0x39) for GCN 1.0/1.1; 45 (0x2d) for GCN 1.2<br />
+Opcode VOP3A: 441 (0x1b9) for GCN 1.0/1.1; 365 (0x16d) for GCN 1.2<br />
+Syntax: V_FFBH_U32 VDST, SRC0<br />
+Description: Find last one bit in SRC0. If found, store number of skipped bits to VDST,
+otherwise set VDST to -1.<br />
+Operation:<br />
+<code>VDST = -1
+for (INT8 i = 31; i &gt;= 0; i--)
+    if ((1U&lt;&lt;i) &amp; SRC0) != 0)
+    { VDST = 31-i; break; }</code></p>
+<h4>V_FFBL_B32</h4>
+<p>Opcode VOP1: 58 (0x3a) for GCN 1.0/1.1; 46 (0x2e) for GCN 1.2<br />
+Opcode VOP3A: 442 (0x1ba) for GCN 1.0/1.1; 366 (0x16e) for GCN 1.2<br />
+Syntax: V_FFBL_B32 VDST, SRC0<br />
+Description: Find first one bit in SRC0. If found, store number of bit to VDST,
+otherwise set VDST to -1.<br />
+Operation:<br />
+<code>VDST = -1
+for (UINT8 i = 0; i &lt; 32; i++)
+    if ((1U&lt;&lt;i) &amp; SRC0) != 0)
+    { VDST = i; break; }</code></p>
+<h4>V_FFBH_I32</h4>
+<p>Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2<br />
+Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2<br />
+Syntax: V_FFBH_I32 VDST, SRC0<br />
+Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits
+to VDST, otherwise set VDST to -1.<br />
+Operation:<br />
+<code>VDST = -1
+UINT32 bitval = (INT32)SRC0&gt;=0 ? 1 : 0
+for (INT8 i = 31; i &gt;= 0; i--)
+    if ((1U&lt;&lt;i) &amp; SRC0) == (bitval&lt;&lt;i))
+    { VDST = 31-i; break; }</code></p>
 <h4>V_FLOOR_F32</h4>
 <p>Opcode VOP1: 36 (0x24) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
@@ -1361 +1402 @@
 Syntax: V_NOP<br />
 Description: Do nothing.</p>
+<h4>V_NOT_B32</h4>
+<p>Opcode VOP1: 55 (0x37) for GCN 1.0/1.1; 43 (0x2b) for GCN 1.2<br />
+Opcode VOP3A: 439 (0x1b7) for GCN 1.0/1.1; 363 (0x16b) for GCN 1.2<br />
+Syntax: V_NOT_B32 VDST, SRC0<br />
+Description: Do bitwise negation on 32-bit SRC0, and store result to VDST.
+Operation:<br />
+<code>VDST = ~SRC0</code></p>
 <h4>V_RCP_CLAMP_F32</h4>
 <p>Opcode VOP1: 40 (0x28) for GCN 1.0/1.1<br />