Changes between Version 11 and Version 12 of GcnInstrsVop1


Ignore:
Timestamp:
11/29/15 18:00:19 (8 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
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Removed
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  • GcnInstrsVop1

    v11 v12  
    926926<td>48 (0x30)</td>
    927927<td>368 (0x170)</td>
    928 <td>V_FREXP_EXP_I32</td>
     928<td>V_FREXP_EXP_I32_F64</td>
    929929</tr>
    930930<tr>
    931931<td>49 (0x31)</td>
    932932<td>369 (0x171)</td>
    933 <td>V_FREXP_MANT_F6</td>
     933<td>V_FREXP_MANT_F64</td>
    934934</tr>
    935935<tr>
    … …  
    941941<td>51 (0x33)</td>
    942942<td>371 (0x173)</td>
    943 <td>V_FREXP_EXP_I32</td>
     943<td>V_FREXP_EXP_I32_F32</td>
    944944</tr>
    945945<tr>
    946946<td>52 (0x34)</td>
    947947<td>372 (0x174)</td>
    948 <td>V_FREXP_MANT_F3</td>
     948<td>V_FREXP_MANT_F32</td>
    949949</tr>
    950950<tr>
    … …  
    10911091    F += 1.0
    10921092VDST = F</code></p>
     1093<h4>V_CLREXCP</h4>
     1094<p>Opcode VOP1: 65 (0x41) for GCN 1.0/1.1; 53 (0x35) for GCN 1.2<br />
     1095Opcode VOP3A: 449 (0x1c1) for GCN 1.0/1.1; 373 (0x175) for GCN 1.2<br />
     1096Syntax: V_CLREXCP<br />
     1097Description: Clear wave's exception state in SIMD.  </p>
    10931098<h4>V_COS_F32</h4>
    10941099<p>Opcode VOP1: 54 (0x36) for GCN 1.0/1.1; 42 (0x2a) for GCN 1.2<br />
    … …  
    13391344<p>Opcode VOP1: 32 (0x20) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2<br />
    13401345Opcode VOP3A: 416 (0x1a0) for GCN 1.0/1.1; 347 (0x15b) for GCN 1.2<br />
    1341 Syntax: V_FRACT VDST, SRC0<br />
     1346Syntax: V_FRACT_F32 VDST, SRC0<br />
    13421347Description: Get fractional from floating point value SRC0 and store it to VDST.
    13431348Fractional will be computed by subtracting floor(SRC0) from SRC0.
    … …  
    13491354else
    13501355    VDST = NAN * SIGN(SF)</code></p>
     1356<h4>V_FRACT_F64</h4>
     1357<p>Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2<br />
     1358Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2<br />
     1359Syntax: V_FRACT_F64 VDST(2), SRC0(2)<br />
     1360Description: Get fractional from double floating point value SRC0 and store it to VDST.
     1361Fractional will be computed by subtracting floor(SRC0) from SRC0.
     1362If SRC0 is infinity or NaN then NaN with proper sign is stored to VDST.<br />
     1363Operation:<br />
     1364<code>FLOAT SD = ASDOUBLE(SRC0)
     1365if (ABS(SD)!=NAN &amp;&amp; SD!=-INF &amp;&amp; SD!=INF)
     1366    VDST = SD - FLOOR(ASDOUBLE(SD))
     1367else
     1368    VDST = NAN * SIGN(SD)</code></p>
     1369<h4>V_FREXP_EXP_I32_F32</h4>
     1370<p>Opcode VOP1: 63 (0x3f) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2<br />
     1371Opcode VOP3A: 447 (0x1bf) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2<br />
     1372Syntax: V_FREXP_EXP_I32_F32 VDST, SRC0<br />
     1373Description: Get exponent minus 1 from single FP value SRC0, and store that exponent to VDST.
     1374This instruction realizes frexp function.
     1375If SRC0 is infinity or NAN then store -1 to VDST.<br />
     1376Operation:<br />
     1377<code>FLOAT SF = ASFLOAT(SRC0)
     1378if (ABS(SF) != INF || ABS(SF) != NAN)
     1379    VDST = FREXP_EXP(SF)
     1380else
     1381    VDST = -1</code></p>
     1382<h4>V_FREXP_EXP_I32_F64</h4>
     1383<p>Opcode VOP1: 60 (0x3c) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2<br />
     1384Opcode VOP3A: 444 (0x1bc) for GCN 1.0/1.1; 368 (0x170) for GCN 1.2<br />
     1385Syntax: V_FREXP_EXP_I32_F64 VDST, SRC0(2)<br />
     1386Description: Get exponent minus 1 from double FP value SRC0, and store that exponent to VDST.
     1387This instruction realizes frexp function.
     1388If SRC0 is infinity or NAN then store -1 to VDST.<br />
     1389Operation:<br />
     1390<code>DOUBLE SD = ASDOUBLE(SRC0)
     1391if (ABS(SD) != INF || ABS(SD) != NAN)
     1392    VDST = FREXP_EXP(SD)
     1393else
     1394    VDST = -1</code></p>
     1395<h4>V_FREXP_MANT_F32</h4>
     1396<p>Opcode VOP1: 64 (0x40) for GCN 1.0/1.1; 52 (0x34) for GCN 1.2<br />
     1397Opcode VOP3A: 448 (0x1c0) for GCN 1.0/1.1; 372 (0x174) for GCN 1.2<br />
     1398Syntax: V_FREXP_MANT_F32 VDST, SRC0<br />
     1399Description: Get mantisa from double FP value SRC0, and store it to VDST. Mantisa includes
     1400sign of input. If SRC0 is infinity then store -NAN to VDST.<br />
     1401Operation:<br />
     1402<code>FLOAT SF = ASFLOAT(SRC0)
     1403if (ABS(SF) == INF)
     1404    VDST = -NAN
     1405else if (ABS(SF) != NAN)
     1406    VDST = FREXP_MANT(SF) * SIGN(SF)
     1407else
     1408    VDST = NAN * SIGN(SF)</code></p>
     1409<h4>V_FREXP_MANT_F64</h4>
     1410<p>Opcode VOP1: 61 (0x3d) for GCN 1.0/1.1; 49 (0x31) for GCN 1.2<br />
     1411Opcode VOP3A: 445 (0x1bd) for GCN 1.0/1.1; 369 (0x171) for GCN 1.2<br />
     1412Syntax: V_FREXP_MANT_F64 VDST(2), SRC0(2)<br />
     1413Description: Get mantisa from double FP value SRC0, and store it to VDST. Mantisa includes
     1414sign of input. If SRC0 is infinity then store -NAN to VDST.<br />
     1415Operation:<br />
     1416<code>DOUBLE SD = ASDOUBLE(SRC0)
     1417if (ABS(SD) == INF)
     1418    VDST = -NAN
     1419else if (ABS(SD) != NAN)
     1420    VDST = FREXP_MANT(SD) * SIGN(SD)
     1421else
     1422    VDST = NAN * SIGN(SD)</code></p>
    13511423<h4>V_LOG_CLAMP_F32</h4>
    13521424<p>Opcode VOP1: 38 (0x26) for GCN 1.0/1.1<br />
    … …  
    13701442}</code></p>
    13711443<h4>V_LOG_F32</h4>
    1372 <p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 2.0<br />
    1373 Opcode VOP3A: 422 (0x1a6) for GCN 1.0/1.1; 353 (0x161) for GCN 2.0<br />
     1444<p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
     1445Opcode VOP3A: 422 (0x1a6) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2<br />
    13741446Syntax: V_LOG_F32 VDST, SRC0<br />
    13751447Description: Approximate logarithm of base 2 from floating point value SRC0, and store result
    … …  
    13971469Operation:<br />
    13981470<code>VDST = SRC0</code></p>
     1471<h4>V_MOVRELD_B32</h4>
     1472<p>Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x35) for GCN 1.2<br />
     1473Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x175) for GCN 1.2<br />
     1474Syntax: V_MOVRELD VDST, VSRC0<br />
     1475Description: Move SRC0 to VGPR[VDST_NUMBER+M0].<br />
     1476Operation:<br />
     1477<code>VGPR[VDST_NUMBER+M0] = SRC0</code></p>
     1478<h4>V_MOVRELS_B32</h4>
     1479<p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2<br />
     1480Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2<br />
     1481Syntax: V_MOVRELS VDST, VSRC0<br />
     1482Description: Move SRC0[SRC0_NUMBER+M0] to VDST.<br />
     1483Operation:<br />
     1484<code>VDST = VGPR[SRC0_NUMBER+M0]</code></p>
     1485<h4>V_MOVRELSD_B32</h4>
     1486<p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2<br />
     1487Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2<br />
     1488Syntax: V_MOVRELSD VDST, VSRC0<br />
     1489Description: Move SRC0[SRC0_NUMBER+M0] to VGPR[VDST_NUMBER+M0].<br />
     1490Operation:<br />
     1491<code>VGPR[VDST_NUMBER+M0] = VGPR[SRC0_NUMBER+M0]</code></p>
    13991492<h4>V_NOP</h4>
    14001493<p>Opcode VOP1: 0 (0x0)<br />
    … …  
    14311524    VDST = SIGN(ASDOUBLE(VDST)) * MAX_DOUBLE</code></p>
    14321525<h4>V_RCP_F32</h4>
    1433 <p>Opcode VOP1: 42 (0x2a) for GCN 1.0/1.1; 34 (0x22) for GCN 2.0<br />
    1434 Opcode VOP3A: 426 (0x1aa) for GCN 1.0/1.1; 354 (0x162) for GCN 2.0<br />
     1526<p>Opcode VOP1: 42 (0x2a) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br />
     1527Opcode VOP3A: 426 (0x1aa) for GCN 1.0/1.1; 354 (0x162) for GCN 1.2<br />
    14351528Syntax: V_RCP_F32 VDST, SRC0<br />
    14361529Description: Approximate reciprocal from floating point value SRC0 and store it to VDST.
    … …  
    14391532<code>VDST = APPROX_RCP(ASFLOAT(SRC0))</code></p>
    14401533<h4>V_RCP_F64</h4>
    1441 <p>Opcode VOP1: 47 (0x2f) for GCN 1.0/1.1; 37 (0x25) for GCN 2.0<br />
    1442 Opcode VOP3A: 431 (0x1af) for GCN 1.0/1.1; 357 (0x165) for GCN 2.0<br />
     1534<p>Opcode VOP1: 47 (0x2f) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2<br />
     1535Opcode VOP3A: 431 (0x1af) for GCN 1.0/1.1; 357 (0x165) for GCN 1.2<br />
    14431536Syntax: V_RCP_F64 VDST(2), SRC0(2)<br />
    14441537Description: Approximate reciprocal from double FP value SRC0 and store it to VDST.
    … …  
    14471540<code>VDST = APPROX_RCP(ASDOUBLE(SRC0))</code></p>
    14481541<h4>V_RCP_IFLAG_F32</h4>
    1449 <p>Opcode VOP1: 43 (0x2b) for GCN 1.0/1.1; 35 (0x23) for GCN 2.0<br />
    1450 Opcode VOP3A: 427 (0x1ab) for GCN 1.0/1.1; 355 (0x163) for GCN 2.0<br />
     1542<p>Opcode VOP1: 43 (0x2b) for GCN 1.0/1.1; 35 (0x23) for GCN 1.2<br />
     1543Opcode VOP3A: 427 (0x1ab) for GCN 1.0/1.1; 355 (0x163) for GCN 1.2<br />
    14511544Syntax: V_RCP_IFLAG_F32 VDST, SRC0<br />
    14521545Description: Approximate reciprocal from floating point value SRC0 and store it to VDST.
    … …  
    15161609    VDST = MAX_DOUBLE</code></p>
    15171610<h4>V_RSQ_F32</h4>
    1518 <p>Opcode VOP1: 46 (0x2e) for GCN 1.0/1.1; 36 (0x24) for GCN 2.0<br />
    1519 Opcode VOP3A: 430 (0x1ae) for GCN 1.0/1.1; 356 (0x164) for GCN 2.0<br />
     1611<p>Opcode VOP1: 46 (0x2e) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
     1612Opcode VOP3A: 430 (0x1ae) for GCN 1.0/1.1; 356 (0x164) for GCN 1.2<br />
    15201613Syntax: V_RSQ_F32 VDST, SRC0<br />
    15211614Description: Approximate reciprocal square root from floating point value SRC0 and
    … …  
    15251618<code>VDST = APPROX_RSQRT(ASFLOAT(SRC0))</code></p>
    15261619<h4>V_RSQ_F64</h4>
    1527 <p>Opcode VOP1: 49 (0x31) for GCN 1.0/1.1; 38 (0x26) for GCN 2.0<br />
    1528 Opcode VOP3A: 433 (0x1b1) for GCN 1.0/1.1; 358 (0x166) for GCN 2.0<br />
     1620<p>Opcode VOP1: 49 (0x31) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2<br />
     1621Opcode VOP3A: 433 (0x1b1) for GCN 1.0/1.1; 358 (0x166) for GCN 1.2<br />
    15291622Syntax: V_RSQ_F64 VDST(2), SRC0(2)<br />
    15301623Description: Approximate reciprocal square root from double floating point value SRC0 and