Changes between Version 12 and Version 13 of GcnInstrsVop1


Ignore:
Timestamp:
Nov 29, 2015, 9:00:17 PM (4 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVop1

    v12 v13  
    10861086(ceilling), and store result to VDST. Implemented by flooring.
    10871087If SRC0 is infinity or NaN then copy SRC0 to VDST.<br />
    1088 Operation:
     1088Operation:<br />
    10891089<code>FLOAT F = FLOOR(ASFLOAT(SRC0))
    10901090if (ASFLOAT(SRC0) &gt; 0.0 &amp;&amp; ASFLOAT(SRC0) != F)
     
    13101310    if ((1U&lt;&lt;i) &amp; SRC0) != 0)
    13111311    { VDST = 31-i; break; }</code></p>
     1312<h4>V_FFBH_I32</h4>
     1313<p>Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2<br />
     1314Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2<br />
     1315Syntax: V_FFBH_I32 VDST, SRC0<br />
     1316Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits
     1317to VDST, otherwise set VDST to -1.<br />
     1318Operation:<br />
     1319<code>VDST = -1
     1320UINT32 bitval = (INT32)SRC0&gt;=0 ? 1 : 0
     1321for (INT8 i = 31; i &gt;= 0; i--)
     1322    if ((1U&lt;&lt;i) &amp; SRC0) == (bitval&lt;&lt;i))
     1323    { VDST = 31-i; break; }</code></p>
    13121324<h4>V_FFBL_B32</h4>
    13131325<p>Opcode VOP1: 58 (0x3a) for GCN 1.0/1.1; 46 (0x2e) for GCN 1.2<br />
     
    13211333    if ((1U&lt;&lt;i) &amp; SRC0) != 0)
    13221334    { VDST = i; break; }</code></p>
    1323 <h4>V_FFBH_I32</h4>
    1324 <p>Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2<br />
    1325 Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2<br />
    1326 Syntax: V_FFBH_I32 VDST, SRC0<br />
    1327 Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits
    1328 to VDST, otherwise set VDST to -1.<br />
    1329 Operation:<br />
    1330 <code>VDST = -1
    1331 UINT32 bitval = (INT32)SRC0&gt;=0 ? 1 : 0
    1332 for (INT8 i = 31; i &gt;= 0; i--)
    1333     if ((1U&lt;&lt;i) &amp; SRC0) == (bitval&lt;&lt;i))
    1334     { VDST = 31-i; break; }</code></p>
    13351335<h4>V_FLOOR_F32</h4>
    13361336<p>Opcode VOP1: 36 (0x24) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
    13371337Opcode VOP3A: 420 (0x1a4) for GCN 1.0/1.1; 351 (0x15f) for GCN 1.2<br />
    13381338Syntax: V_FLOOR_F32 VDST, SRC0<br />
    1339 Description: Truncate floating point valu from SRC0 with rounding to positive infinity
     1339Description: Truncate floating point value SRC0 with rounding to positive infinity
    13401340(flooring), and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br />
    1341 Operation:
     1341Operation:<br />
    13421342<code>VDST = FLOOR(ASFLOAT(SRC0))</code></p>
    13431343<h4>V_FRACT_F32</h4>
     
    13551355    VDST = NAN * SIGN(SF)</code></p>
    13561356<h4>V_FRACT_F64</h4>
    1357 <p>Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2<br />
    1358 Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2<br />
     1357<p>Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 52 (0x32) for GCN 1.2<br />
     1358Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 372 (0x172) for GCN 1.2<br />
    13591359Syntax: V_FRACT_F64 VDST(2), SRC0(2)<br />
    13601360Description: Get fractional from double floating point value SRC0 and store it to VDST.
     
    13711371Opcode VOP3A: 447 (0x1bf) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2<br />
    13721372Syntax: V_FREXP_EXP_I32_F32 VDST, SRC0<br />
    1373 Description: Get exponent minus 1 from single FP value SRC0, and store that exponent to VDST.
     1373Description: Get exponent plus 1 from single FP value SRC0, and store that exponent to VDST.
    13741374This instruction realizes frexp function.
    13751375If SRC0 is infinity or NAN then store -1 to VDST.<br />
     
    13841384Opcode VOP3A: 444 (0x1bc) for GCN 1.0/1.1; 368 (0x170) for GCN 1.2<br />
    13851385Syntax: V_FREXP_EXP_I32_F64 VDST, SRC0(2)<br />
    1386 Description: Get exponent minus 1 from double FP value SRC0, and store that exponent to VDST.
     1386Description: Get exponent plus 1 from double FP value SRC0, and store that exponent to VDST.
    13871387This instruction realizes frexp function.
    13881388If SRC0 is infinity or NAN then store -1 to VDST.<br />
     
    14431443<h4>V_LOG_F32</h4>
    14441444<p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
    1445 Opcode VOP3A: 422 (0x1a6) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2<br />
     1445Opcode VOP3A: 423 (0x1a7) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2<br />
    14461446Syntax: V_LOG_F32 VDST, SRC0<br />
    14471447Description: Approximate logarithm of base 2 from floating point value SRC0, and store result
     
    14561456else
    14571457    VDST = APPROX_LOG2(F)</code></p>
     1458<h4>V_MOV_B32</h4>
     1459<p>Opcode VOP1: 1 (0x1)<br />
     1460Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br />
     1461Syntax: V_MOV_B32 VDST, SRC0<br />
     1462Description: Move SRC0 into VDST.<br />
     1463Operation:<br />
     1464<code>VDST = SRC0</code></p>
    14581465<h4>V_MOV_FED_B32</h4>
    14591466<p>Opcode VOP1: 9 (0x9)<br />
     
    14621469Description: Introduce edc double error upon write to dest vgpr without causing an exception
    14631470(???).</p>
    1464 <h4>V_MOV_B32</h4>
    1465 <p>Opcode VOP1: 1 (0x1)<br />
    1466 Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br />
    1467 Syntax: V_MOV_B32 VDST, SRC0<br />
    1468 Description: Move SRC0 into VDST.<br />
    1469 Operation:<br />
    1470 <code>VDST = SRC0</code></p>
    14711471<h4>V_MOVRELD_B32</h4>
    1472 <p>Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x35) for GCN 1.2<br />
    1473 Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x175) for GCN 1.2<br />
     1472<p>Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x34) for GCN 1.2<br />
     1473Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x174) for GCN 1.2<br />
    14741474Syntax: V_MOVRELD VDST, VSRC0<br />
    14751475Description: Move SRC0 to VGPR[VDST_NUMBER+M0].<br />
     
    14771477<code>VGPR[VDST_NUMBER+M0] = SRC0</code></p>
    14781478<h4>V_MOVRELS_B32</h4>
    1479 <p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2<br />
    1480 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2<br />
     1479<p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x35) for GCN 1.2<br />
     1480Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x175) for GCN 1.2<br />
    14811481Syntax: V_MOVRELS VDST, VSRC0<br />
    14821482Description: Move SRC0[SRC0_NUMBER+M0] to VDST.<br />
     
    14841484<code>VDST = VGPR[SRC0_NUMBER+M0]</code></p>
    14851485<h4>V_MOVRELSD_B32</h4>
    1486 <p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2<br />
    1487 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2<br />
     1486<p>Opcode VOP1: 68 (0x44) for GCN 1.0/1.1; 56 (0x36) for GCN 1.2<br />
     1487Opcode VOP3A: 452 (0x1c4) for GCN 1.0/1.1; 376 (0x176) for GCN 1.2<br />
    14881488Syntax: V_MOVRELSD VDST, VSRC0<br />
    14891489Description: Move SRC0[SRC0_NUMBER+M0] to VGPR[VDST_NUMBER+M0].<br />
     
    14991499Opcode VOP3A: 439 (0x1b7) for GCN 1.0/1.1; 363 (0x16b) for GCN 1.2<br />
    15001500Syntax: V_NOT_B32 VDST, SRC0<br />
    1501 Description: Do bitwise negation on 32-bit SRC0, and store result to VDST.
     1501Description: Do bitwise negation on 32-bit SRC0, and store result to VDST.<br />
    15021502Operation:<br />
    15031503<code>VDST = ~SRC0</code></p>