Changes between Version 12 and Version 13 of GcnInstrsVop1
- Timestamp:
- 11/29/15 21:00:17 (8 years ago)
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GcnInstrsVop1
v12 v13 1086 1086 (ceilling), and store result to VDST. Implemented by flooring. 1087 1087 If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1088 Operation: 1088 Operation:<br /> 1089 1089 <code>FLOAT F = FLOOR(ASFLOAT(SRC0)) 1090 1090 if (ASFLOAT(SRC0) > 0.0 && ASFLOAT(SRC0) != F) … … 1310 1310 if ((1U<<i) & SRC0) != 0) 1311 1311 { VDST = 31-i; break; }</code></p> 1312 <h4>V_FFBH_I32</h4> 1313 <p>Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2<br /> 1314 Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2<br /> 1315 Syntax: V_FFBH_I32 VDST, SRC0<br /> 1316 Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits 1317 to VDST, otherwise set VDST to -1.<br /> 1318 Operation:<br /> 1319 <code>VDST = -1 1320 UINT32 bitval = (INT32)SRC0>=0 ? 1 : 0 1321 for (INT8 i = 31; i >= 0; i--) 1322 if ((1U<<i) & SRC0) == (bitval<<i)) 1323 { VDST = 31-i; break; }</code></p> 1312 1324 <h4>V_FFBL_B32</h4> 1313 1325 <p>Opcode VOP1: 58 (0x3a) for GCN 1.0/1.1; 46 (0x2e) for GCN 1.2<br /> … … 1321 1333 if ((1U<<i) & SRC0) != 0) 1322 1334 { VDST = i; break; }</code></p> 1323 <h4>V_FFBH_I32</h4>1324 <p>Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2<br />1325 Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2<br />1326 Syntax: V_FFBH_I32 VDST, SRC0<br />1327 Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits1328 to VDST, otherwise set VDST to -1.<br />1329 Operation:<br />1330 <code>VDST = -11331 UINT32 bitval = (INT32)SRC0>=0 ? 1 : 01332 for (INT8 i = 31; i >= 0; i--)1333 if ((1U<<i) & SRC0) == (bitval<<i))1334 { VDST = 31-i; break; }</code></p>1335 1335 <h4>V_FLOOR_F32</h4> 1336 1336 <p>Opcode VOP1: 36 (0x24) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br /> 1337 1337 Opcode VOP3A: 420 (0x1a4) for GCN 1.0/1.1; 351 (0x15f) for GCN 1.2<br /> 1338 1338 Syntax: V_FLOOR_F32 VDST, SRC0<br /> 1339 Description: Truncate floating point valu fromSRC0 with rounding to positive infinity1339 Description: Truncate floating point value SRC0 with rounding to positive infinity 1340 1340 (flooring), and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1341 Operation: 1341 Operation:<br /> 1342 1342 <code>VDST = FLOOR(ASFLOAT(SRC0))</code></p> 1343 1343 <h4>V_FRACT_F32</h4> … … 1355 1355 VDST = NAN * SIGN(SF)</code></p> 1356 1356 <h4>V_FRACT_F64</h4> 1357 <p>Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 5 1 (0x33) for GCN 1.2<br />1358 Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 37 1 (0x173) for GCN 1.2<br />1357 <p>Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 52 (0x32) for GCN 1.2<br /> 1358 Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 372 (0x172) for GCN 1.2<br /> 1359 1359 Syntax: V_FRACT_F64 VDST(2), SRC0(2)<br /> 1360 1360 Description: Get fractional from double floating point value SRC0 and store it to VDST. … … 1371 1371 Opcode VOP3A: 447 (0x1bf) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2<br /> 1372 1372 Syntax: V_FREXP_EXP_I32_F32 VDST, SRC0<br /> 1373 Description: Get exponent minus 1 from single FP value SRC0, and store that exponent to VDST.1373 Description: Get exponent plus 1 from single FP value SRC0, and store that exponent to VDST. 1374 1374 This instruction realizes frexp function. 1375 1375 If SRC0 is infinity or NAN then store -1 to VDST.<br /> … … 1384 1384 Opcode VOP3A: 444 (0x1bc) for GCN 1.0/1.1; 368 (0x170) for GCN 1.2<br /> 1385 1385 Syntax: V_FREXP_EXP_I32_F64 VDST, SRC0(2)<br /> 1386 Description: Get exponent minus 1 from double FP value SRC0, and store that exponent to VDST.1386 Description: Get exponent plus 1 from double FP value SRC0, and store that exponent to VDST. 1387 1387 This instruction realizes frexp function. 1388 1388 If SRC0 is infinity or NAN then store -1 to VDST.<br /> … … 1443 1443 <h4>V_LOG_F32</h4> 1444 1444 <p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br /> 1445 Opcode VOP3A: 42 2 (0x1a6) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2<br />1445 Opcode VOP3A: 423 (0x1a7) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2<br /> 1446 1446 Syntax: V_LOG_F32 VDST, SRC0<br /> 1447 1447 Description: Approximate logarithm of base 2 from floating point value SRC0, and store result … … 1456 1456 else 1457 1457 VDST = APPROX_LOG2(F)</code></p> 1458 <h4>V_MOV_B32</h4> 1459 <p>Opcode VOP1: 1 (0x1)<br /> 1460 Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br /> 1461 Syntax: V_MOV_B32 VDST, SRC0<br /> 1462 Description: Move SRC0 into VDST.<br /> 1463 Operation:<br /> 1464 <code>VDST = SRC0</code></p> 1458 1465 <h4>V_MOV_FED_B32</h4> 1459 1466 <p>Opcode VOP1: 9 (0x9)<br /> … … 1462 1469 Description: Introduce edc double error upon write to dest vgpr without causing an exception 1463 1470 (???).</p> 1464 <h4>V_MOV_B32</h4>1465 <p>Opcode VOP1: 1 (0x1)<br />1466 Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br />1467 Syntax: V_MOV_B32 VDST, SRC0<br />1468 Description: Move SRC0 into VDST.<br />1469 Operation:<br />1470 <code>VDST = SRC0</code></p>1471 1471 <h4>V_MOVRELD_B32</h4> 1472 <p>Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x3 5) for GCN 1.2<br />1473 Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x17 5) for GCN 1.2<br />1472 <p>Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x34) for GCN 1.2<br /> 1473 Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x174) for GCN 1.2<br /> 1474 1474 Syntax: V_MOVRELD VDST, VSRC0<br /> 1475 1475 Description: Move SRC0 to VGPR[VDST_NUMBER+M0].<br /> … … 1477 1477 <code>VGPR[VDST_NUMBER+M0] = SRC0</code></p> 1478 1478 <h4>V_MOVRELS_B32</h4> 1479 <p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x3 6) for GCN 1.2<br />1480 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x17 6) for GCN 1.2<br />1479 <p>Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x35) for GCN 1.2<br /> 1480 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x175) for GCN 1.2<br /> 1481 1481 Syntax: V_MOVRELS VDST, VSRC0<br /> 1482 1482 Description: Move SRC0[SRC0_NUMBER+M0] to VDST.<br /> … … 1484 1484 <code>VDST = VGPR[SRC0_NUMBER+M0]</code></p> 1485 1485 <h4>V_MOVRELSD_B32</h4> 1486 <p>Opcode VOP1: 6 7 (0x43) for GCN 1.0/1.1; 55(0x36) for GCN 1.2<br />1487 Opcode VOP3A: 45 1 (0x1c3) for GCN 1.0/1.1; 375(0x176) for GCN 1.2<br />1486 <p>Opcode VOP1: 68 (0x44) for GCN 1.0/1.1; 56 (0x36) for GCN 1.2<br /> 1487 Opcode VOP3A: 452 (0x1c4) for GCN 1.0/1.1; 376 (0x176) for GCN 1.2<br /> 1488 1488 Syntax: V_MOVRELSD VDST, VSRC0<br /> 1489 1489 Description: Move SRC0[SRC0_NUMBER+M0] to VGPR[VDST_NUMBER+M0].<br /> … … 1499 1499 Opcode VOP3A: 439 (0x1b7) for GCN 1.0/1.1; 363 (0x16b) for GCN 1.2<br /> 1500 1500 Syntax: V_NOT_B32 VDST, SRC0<br /> 1501 Description: Do bitwise negation on 32-bit SRC0, and store result to VDST. 1501 Description: Do bitwise negation on 32-bit SRC0, and store result to VDST.<br /> 1502 1502 Operation:<br /> 1503 1503 <code>VDST = ~SRC0</code></p>