Changes between Version 1 and Version 2 of GcnInstrsVop1


Ignore:
Timestamp:
11/26/15 19:00:15 (8 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • GcnInstrsVop1

    v1 v2  
    373373<td>23 (0x17)</td>
    374374<td>407 (0x197)</td>
    375 <td>✓</td>
     375<td></td>
    376376<td>✓</td>
    377377<td>V_TRUNC_F64</td>
    … …  
    380380<td>24 (0x18)</td>
    381381<td>408 (0x198)</td>
    382 <td>✓</td>
     382<td></td>
    383383<td>✓</td>
    384384<td>V_CEIL_F64</td>
    … …  
    387387<td>25 (0x19)</td>
    388388<td>409 (0x199)</td>
    389 <td>✓</td>
     389<td></td>
    390390<td>✓</td>
    391391<td>V_RNDNE_F64</td>
    … …  
    394394<td>26 (0x1a)</td>
    395395<td>410 (0x19a)</td>
    396 <td>✓</td>
     396<td></td>
    397397<td>✓</td>
    398398<td>V_FLOOR_F64</td>
    … …  
    673673</tbody>
    674674</table>
     675<p>List of the instructions by opcode (GCN 1.2):</p>
     676<table>
     677<thead>
     678<tr>
     679<th>Opcode</th>
     680<th>Opcode(VOP3)</th>
     681<th>Mnemonic</th>
     682</tr>
     683</thead>
     684<tbody>
     685<tr>
     686<td>0 (0x0)</td>
     687<td>320 (0x140)</td>
     688<td>V_NOP</td>
     689</tr>
     690<tr>
     691<td>1 (0x1)</td>
     692<td>321 (0x141)</td>
     693<td>V_MOV_B32</td>
     694</tr>
     695<tr>
     696<td>2 (0x2)</td>
     697<td>322 (0x142)</td>
     698<td>V_READFIRSTLANE_B32</td>
     699</tr>
     700<tr>
     701<td>3 (0x3)</td>
     702<td>323 (0x143)</td>
     703<td>V_CVT_I32_F64</td>
     704</tr>
     705<tr>
     706<td>4 (0x4)</td>
     707<td>324 (0x144)</td>
     708<td>V_CVT_F64_I32</td>
     709</tr>
     710<tr>
     711<td>5 (0x5)</td>
     712<td>325 (0x145)</td>
     713<td>V_CVT_F32_I32</td>
     714</tr>
     715<tr>
     716<td>6 (0x6)</td>
     717<td>326 (0x146)</td>
     718<td>V_CVT_F32_U32</td>
     719</tr>
     720<tr>
     721<td>7 (0x7)</td>
     722<td>327 (0x147)</td>
     723<td>V_CVT_U32_F32</td>
     724</tr>
     725<tr>
     726<td>8 (0x8)</td>
     727<td>328 (0x148)</td>
     728<td>V_CVT_I32_F32</td>
     729</tr>
     730<tr>
     731<td>9 (0x9)</td>
     732<td>329 (0x149)</td>
     733<td>V_MOV_FED_B32</td>
     734</tr>
     735<tr>
     736<td>10 (0xa)</td>
     737<td>330 (0x14a)</td>
     738<td>V_CVT_F16_F32</td>
     739</tr>
     740<tr>
     741<td>11 (0xb)</td>
     742<td>331 (0x14b)</td>
     743<td>V_CVT_F32_F16</td>
     744</tr>
     745<tr>
     746<td>12 (0xc)</td>
     747<td>332 (0x14c)</td>
     748<td>V_CVT_RPI_I32_F32</td>
     749</tr>
     750<tr>
     751<td>13 (0xd)</td>
     752<td>333 (0x14d)</td>
     753<td>V_CVT_FLR_I32_F32</td>
     754</tr>
     755<tr>
     756<td>14 (0xe)</td>
     757<td>334 (0x14e)</td>
     758<td>V_CVT_OFF_F32_I4</td>
     759</tr>
     760<tr>
     761<td>15 (0xf)</td>
     762<td>335 (0x14f)</td>
     763<td>V_CVT_F32_F64</td>
     764</tr>
     765<tr>
     766<td>16 (0x10)</td>
     767<td>336 (0x150)</td>
     768<td>V_CVT_F64_F32</td>
     769</tr>
     770<tr>
     771<td>17 (0x11)</td>
     772<td>337 (0x151)</td>
     773<td>V_CVT_F32_UBYTE0</td>
     774</tr>
     775<tr>
     776<td>18 (0x12)</td>
     777<td>338 (0x152)</td>
     778<td>V_CVT_F32_UBYTE1</td>
     779</tr>
     780<tr>
     781<td>19 (0x13)</td>
     782<td>339 (0x153)</td>
     783<td>V_CVT_F32_UBYTE2</td>
     784</tr>
     785<tr>
     786<td>20 (0x14)</td>
     787<td>340 (0x154)</td>
     788<td>V_CVT_F32_UBYTE3</td>
     789</tr>
     790<tr>
     791<td>21 (0x15)</td>
     792<td>341 (0x155)</td>
     793<td>V_CVT_U32_F64</td>
     794</tr>
     795<tr>
     796<td>22 (0x16)</td>
     797<td>342 (0x156)</td>
     798<td>V_CVT_F64_U32</td>
     799</tr>
     800<tr>
     801<td>23 (0x17)</td>
     802<td>343 (0x157)</td>
     803<td>V_TRUNC_F64</td>
     804</tr>
     805<tr>
     806<td>24 (0x18)</td>
     807<td>344 (0x158)</td>
     808<td>V_CEIL_F64</td>
     809</tr>
     810<tr>
     811<td>25 (0x19)</td>
     812<td>345 (0x159)</td>
     813<td>V_RNDNE_F64</td>
     814</tr>
     815<tr>
     816<td>26 (0x1a)</td>
     817<td>346 (0x15a)</td>
     818<td>V_FLOOR_F64</td>
     819</tr>
     820<tr>
     821<td>27 (0x1b)</td>
     822<td>347 (0x15b)</td>
     823<td>V_FRACT_F32</td>
     824</tr>
     825<tr>
     826<td>28 (0x1c)</td>
     827<td>348 (0x15c)</td>
     828<td>V_TRUNC_F32</td>
     829</tr>
     830<tr>
     831<td>29 (0x1d)</td>
     832<td>349 (0x15d)</td>
     833<td>V_CEIL_F32</td>
     834</tr>
     835<tr>
     836<td>30 (0x1e)</td>
     837<td>350 (0x15e)</td>
     838<td>V_RNDNE_F32</td>
     839</tr>
     840<tr>
     841<td>31 (0x1f)</td>
     842<td>351 (0x15f)</td>
     843<td>V_FLOOR_F32</td>
     844</tr>
     845<tr>
     846<td>32 (0x20)</td>
     847<td>352 (0x160)</td>
     848<td>V_EXP_F32</td>
     849</tr>
     850<tr>
     851<td>33 (0x21)</td>
     852<td>353 (0x161)</td>
     853<td>V_LOG_F32</td>
     854</tr>
     855<tr>
     856<td>34 (0x22)</td>
     857<td>354 (0x162)</td>
     858<td>V_RCP_F32</td>
     859</tr>
     860<tr>
     861<td>35 (0x23)</td>
     862<td>355 (0x163)</td>
     863<td>V_RCP_IFLAG_F32</td>
     864</tr>
     865<tr>
     866<td>36 (0x24)</td>
     867<td>356 (0x164)</td>
     868<td>V_RSQ_F32</td>
     869</tr>
     870<tr>
     871<td>37 (0x25)</td>
     872<td>357 (0x165)</td>
     873<td>V_RCP_F64</td>
     874</tr>
     875<tr>
     876<td>38 (0x26)</td>
     877<td>358 (0x166)</td>
     878<td>V_RSQ_F64</td>
     879</tr>
     880<tr>
     881<td>39 (0x27)</td>
     882<td>359 (0x167)</td>
     883<td>V_SQRT_F32</td>
     884</tr>
     885<tr>
     886<td>40 (0x28)</td>
     887<td>360 (0x168)</td>
     888<td>V_SQRT_F64</td>
     889</tr>
     890<tr>
     891<td>41 (0x29)</td>
     892<td>361 (0x169)</td>
     893<td>V_SIN_F32</td>
     894</tr>
     895<tr>
     896<td>42 (0x2a)</td>
     897<td>362 (0x16a)</td>
     898<td>V_COS_F32</td>
     899</tr>
     900<tr>
     901<td>43 (0x2b)</td>
     902<td>363 (0x16b)</td>
     903<td>V_NOT_B32</td>
     904</tr>
     905<tr>
     906<td>44 (0x2c)</td>
     907<td>364 (0x16c)</td>
     908<td>V_BFREV_B32</td>
     909</tr>
     910<tr>
     911<td>45 (0x2d)</td>
     912<td>365 (0x16d)</td>
     913<td>V_FFBH_U32</td>
     914</tr>
     915<tr>
     916<td>46 (0x2e)</td>
     917<td>366 (0x16e)</td>
     918<td>V_FFBL_B32</td>
     919</tr>
     920<tr>
     921<td>47 (0x2f)</td>
     922<td>367 (0x16f)</td>
     923<td>V_FFBH_I32</td>
     924</tr>
     925<tr>
     926<td>48 (0x30)</td>
     927<td>368 (0x170)</td>
     928<td>V_FREXP_EXP_I32</td>
     929</tr>
     930<tr>
     931<td>49 (0x31)</td>
     932<td>369 (0x171)</td>
     933<td>V_FREXP_MANT_F6</td>
     934</tr>
     935<tr>
     936<td>50 (0x32)</td>
     937<td>370 (0x172)</td>
     938<td>V_FRACT_F64</td>
     939</tr>
     940<tr>
     941<td>51 (0x33)</td>
     942<td>371 (0x173)</td>
     943<td>V_FREXP_EXP_I32</td>
     944</tr>
     945<tr>
     946<td>52 (0x34)</td>
     947<td>372 (0x174)</td>
     948<td>V_FREXP_MANT_F3</td>
     949</tr>
     950<tr>
     951<td>53 (0x35)</td>
     952<td>373 (0x175)</td>
     953<td>V_CLREXCP</td>
     954</tr>
     955<tr>
     956<td>54 (0x36)</td>
     957<td>374 (0x176)</td>
     958<td>V_MOVRELD_B32</td>
     959</tr>
     960<tr>
     961<td>55 (0x37)</td>
     962<td>375 (0x177)</td>
     963<td>V_MOVRELS_B32</td>
     964</tr>
     965<tr>
     966<td>56 (0x38)</td>
     967<td>376 (0x178)</td>
     968<td>V_MOVRELSD_B32</td>
     969</tr>
     970<tr>
     971<td>57 (0x39)</td>
     972<td>377 (0x179)</td>
     973<td>V_CVT_F16_U16</td>
     974</tr>
     975<tr>
     976<td>58 (0x3a)</td>
     977<td>378 (0x17a)</td>
     978<td>V_CVT_F16_I16</td>
     979</tr>
     980<tr>
     981<td>59 (0x3b)</td>
     982<td>379 (0x17b)</td>
     983<td>V_CVT_U16_F16</td>
     984</tr>
     985<tr>
     986<td>60 (0x3c)</td>
     987<td>380 (0x17c)</td>
     988<td>V_CVT_I16_F16</td>
     989</tr>
     990<tr>
     991<td>61 (0x3d)</td>
     992<td>381 (0x17d)</td>
     993<td>V_RCP_F16</td>
     994</tr>
     995<tr>
     996<td>62 (0x3e)</td>
     997<td>382 (0x17e)</td>
     998<td>V_SQRT_F16</td>
     999</tr>
     1000<tr>
     1001<td>63 (0x3f)</td>
     1002<td>383 (0x17f)</td>
     1003<td>V_RSQ_F16</td>
     1004</tr>
     1005<tr>
     1006<td>64 (0x40)</td>
     1007<td>384 (0x180)</td>
     1008<td>V_LOG_F16</td>
     1009</tr>
     1010<tr>
     1011<td>65 (0x41)</td>
     1012<td>385 (0x181)</td>
     1013<td>V_EXP_F16</td>
     1014</tr>
     1015<tr>
     1016<td>66 (0x42)</td>
     1017<td>386 (0x182)</td>
     1018<td>V_FREXP_MANT_F16</td>
     1019</tr>
     1020<tr>
     1021<td>67 (0x43)</td>
     1022<td>387 (0x183)</td>
     1023<td>V_FREXP_EXP_I16_F16</td>
     1024</tr>
     1025<tr>
     1026<td>68 (0x44)</td>
     1027<td>388 (0x184)</td>
     1028<td>V_FLOOR_F16</td>
     1029</tr>
     1030<tr>
     1031<td>69 (0x45)</td>
     1032<td>389 (0x185)</td>
     1033<td>V_CEIL_F16</td>
     1034</tr>
     1035<tr>
     1036<td>70 (0x46)</td>
     1037<td>390 (0x186)</td>
     1038<td>V_TRUNC_F16</td>
     1039</tr>
     1040<tr>
     1041<td>71 (0x47)</td>
     1042<td>391 (0x187)</td>
     1043<td>V_RNDNE_F16</td>
     1044</tr>
     1045<tr>
     1046<td>72 (0x48)</td>
     1047<td>392 (0x188)</td>
     1048<td>V_FRACT_F16</td>
     1049</tr>
     1050<tr>
     1051<td>73 (0x49)</td>
     1052<td>393 (0x189)</td>
     1053<td>V_SIN_F16</td>
     1054</tr>
     1055<tr>
     1056<td>74 (0x4a)</td>
     1057<td>394 (0x18a)</td>
     1058<td>V_COS_F16</td>
     1059</tr>
     1060<tr>
     1061<td>75 (0x4b)</td>
     1062<td>395 (0x18b)</td>
     1063<td>V_EXP_LEGACY_F32</td>
     1064</tr>
     1065<tr>
     1066<td>76 (0x4c)</td>
     1067<td>396 (0x18c)</td>
     1068<td>V_LOG_LEGACY_F32</td>
     1069</tr>
     1070</tbody>
     1071</table>
     1072<h3>Instruction set</h3>
     1073<p>Alphabetically sorted instruction list:</p>
     1074<h4>V_NOP</h4>
    6751075}}}