Changes between Version 26 and Version 27 of GcnInstrsVop1
- Timestamp:
- 06/16/17 19:00:24 (5 years ago)
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GcnInstrsVop1
v26 v27 189 189 NOTE: OMOD and CLAMP modifier affects only for instruction that output is 190 190 floating point value.<br /> 191 NOTE: ABS and negation is applied to source operand for any instruction.<br /> 192 NOTE: OMOD modifier doesn't work for half precision (FP16) instructions.</p> 191 NOTE: ABS and negation is applied to source operand for any instruction. </p> 193 192 <p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and 194 193 OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p> … … 1137 1136 Description: Convert single FP value to half floating point value with rounding from 1138 1137 MODE register (single FP rounding mode), and store result to VDST. 1139 If absolute value is too high, then store -/+infinity to VDST.<br /> 1138 If absolute value is too high, then store -/+infinity to VDST. 1139 In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled.<br /> 1140 1140 Operation:<br /> 1141 1141 <code>VDST = CVTHALF(ASFLOAT(SRC0))</code></p> 1142 <h4>V_CVT_F16_U16</h4> 1143 <p>Opcode: VOP1: 57 (0x39) for GCN 1.2<br /> 1144 Opcode VOP3A: 377 (0x179) for GCN 1.2<br /> 1145 Syntax: V_CVT_F16_U16 VDST, SRC0<br /> 1146 Description: Convert 16-bit unsigned valut to half floating point value.<br /> 1147 Operation:<br /> 1148 <code>VDST = (HALF)SRC0</code></p> 1142 1149 <h4>V_CVT_F32_F16</h4> 1143 1150 <p>Opcode VOP1: 11 (0xb)<br /> … … 1145 1152 Syntax: V_CVT_F32_F16 VDST, SRC0<br /> 1146 1153 Description: Convert half FP value to single FP value, and store result to VDST. 1147 <strong>By default, immediate is in FP32 format!</strong>.<br /> 1154 <strong>By default, immediate is in FP32 format!</strong>. 1155 In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled.<br /> 1148 1156 Operation:<br /> 1149 1157 <code>VDST = (FLOAT)(ASHALF(SRC0))</code></p>