Changes between Version 26 and Version 27 of GcnInstrsVop1

Timestamp:

06/16/17 19:00:24 (5 years ago)

Author:

trac

Comment:

--

GcnInstrsVop1

@@ -189 +189 @@
 NOTE: OMOD and CLAMP modifier affects only for instruction that output is
 floating point value.<br />
-NOTE: ABS and negation is applied to source operand for any instruction.<br />
-NOTE: OMOD modifier doesn't work for half precision (FP16) instructions.</p>
+NOTE: ABS and negation is applied to source operand for any instruction.  </p>
 <p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and
 OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p>
@@ -1137 +1136 @@
 Description: Convert single FP value to half floating point value with rounding from
 MODE register (single FP rounding mode), and store result to VDST.
-If absolute value is too high, then store -/+infinity to VDST.<br />
+If absolute value is too high, then store -/+infinity to VDST.
+In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled.<br />
 Operation:<br />
 <code>VDST = CVTHALF(ASFLOAT(SRC0))</code></p>
+<h4>V_CVT_F16_U16</h4>
+<p>Opcode: VOP1: 57 (0x39) for GCN 1.2<br />
+Opcode VOP3A: 377 (0x179) for GCN 1.2<br />
+Syntax: V_CVT_F16_U16 VDST, SRC0<br />
+Description: Convert 16-bit unsigned valut to half floating point value.<br />
+Operation:<br />
+<code>VDST = (HALF)SRC0</code></p>
 <h4>V_CVT_F32_F16</h4>
 <p>Opcode VOP1: 11 (0xb)<br />
@@ -1145 +1152 @@
 Syntax: V_CVT_F32_F16 VDST, SRC0<br />
 Description: Convert half FP value to single FP value, and store result to VDST.
-<strong>By default, immediate is in FP32 format!</strong>.<br />
+<strong>By default, immediate is in FP32 format!</strong>.
+In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled.<br />
 Operation:<br />
 <code>VDST = (FLOAT)(ASHALF(SRC0))</code></p>