Changes between Version 28 and Version 29 of GcnInstrsVop1
 Timestamp:
 Jun 17, 2017, 10:00:25 AM (2 years ago)
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GcnInstrsVop1
v28 v29 1253 1253 else 1254 1254 VDST = (INT32)SF>=0 ? 2147483647 : 2147483648</code></p> 1255 <h4>V_CVT_I16_F16</h4> 1256 <p>Opcode VOP1: 60 (0x3c)<br /> 1257 Opcode VOP3A: 380 (0x17c) for GCN 1.2<br /> 1258 Syntax: V_CVT_I16_F16 VDST, SRC0<br /> 1259 Description: Convert 16bit floating point value from SRC0 to signed 16bit integer, and 1260 store result to VDST. Conversion uses rounding to zero. If value is higher/lower than 1261 maximal/minimal integer then store MAX_INT16/MIN_INT16 to VDST. 1262 If input value is NaN then store 0 to VDST.<br /> 1263 Operation:<br /> 1264 <code>VDST = 0 1265 if (!ISNAN(ASHALF(SRC0))) 1266 VDST = (INT16)MAX(MIN(RNDTZINT(ASHALF(SRC0)), 32767.0), 32768.0)</code></p> 1255 1267 <h4>V_CVT_I32_F32</h4> 1256 1268 <p>Opcode VOP1: 8 (0x8)<br /> … … 1299 1311 else 1300 1312 VDST = (INT32)SF>=0 ? 2147483647 : 2147483648</code></p> 1313 <h4>V_CVT_U16_F16</h4> 1314 <p>Opcode VOP1: 59 (0x3b) for GCN 1.2<br /> 1315 Opcode VOP3A: 379 (0x17b) for GCN 1.2<br /> 1316 Syntax: V_CVT_U16_F16 VDST, SRC0<br /> 1317 Description: Convert 32bit half floating point value from SRC0 to unsigned 16bit integer, 1318 and store result to VDST. Conversion uses rounding to zero. If value is higher than 1319 maximal integer then store MAX_UINT16 to VDST. If input value is NaN then store 0 to VDST.<br /> 1320 Operation:<br /> 1321 <code>VDST = 0 1322 if (!ISNAN(ASHALF(SRC0))) 1323 VDST = (UINT16)MIN(RNDTZINT(ASHALF(SRC0)), 65535.0)</code></p> 1301 1324 <h4>V_CVT_U32_F32</h4> 1302 1325 <p>Opcode VOP1: 7 (0x7)<br /> … … 1323 1346 if (!ISNAN(ASDOUBLE(SRC0))) 1324 1347 VDST = (UINT32)MIN(RNDTZINT(ASDOUBLE(SRC0)), 4294967295.0)</code></p> 1348 <h4>V_EXP_F16</h4> 1349 <p>Opcode VOP1: 65 (0x41) for GCN 1.2<br /> 1350 Opcode VOP3A: 385 (0x181) for GCN 1.2<br /> 1351 Syntax: V_EXP_F16 VDST, SRC0<br /> 1352 Description: Approximate power of two from half FP value SRC0 and store it to VDST. 1353 Instruction always handles dernomals in output regardless floatmode in MODE register.<br /> 1354 Operation:<br /> 1355 <code>VDST = APPROX_POW2(ASHALF(SRC0))</code></p> 1325 1356 <h4>V_EXP_F32</h4> 1326 1357 <p>Opcode VOP1: 37 (0x25) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2<br /> … … 1496 1527 VDST = MAX_FLOAT 1497 1528 }</code></p> 1529 <h4>V_LOG_F16</h4> 1530 <p>Opcode VOP1: 64 (0x40) for GCN 1.2<br /> 1531 Opcode VOP3A: 384 (0x180) for GCN 1.2<br /> 1532 Syntax: V_LOG_F16 VDST, SRC0<br /> 1533 Description: Approximate logarithm of base 2 from half floating point value SRC0, and store 1534 result to VDST. If SRC0 is negative then store NaN to VDST. 1535 This instruction handle denormalized values regardless FLOAT MODE register setup.<br /> 1536 Operation:<br /> 1537 <code>HALF F = ASHALF(SRC0) 1538 if (F==1.0) 1539 VDST = 0.0h 1540 if (F<0.0) 1541 VDST = NaN_F 1542 else 1543 VDST = APPROX_LOG2(F)</code></p> 1498 1544 <h4>V_LOG_F32</h4> 1499 1545 <p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br /> … … 1594 1640 if (ABS(ASDOUBLE(VDST))==INF) 1595 1641 VDST = SIGN(ASDOUBLE(VDST)) * MAX_DOUBLE</code></p> 1642 <h4>V_RCP_F16</h4> 1643 <p>Opcode VOP1: 61 (0x3d) for GCN 1.2<br /> 1644 Opcode VOP3A: 381 (0x17d) for GCN 1.2<br /> 1645 Syntax: V_RCP_F16 VDST, SRC0<br /> 1646 Description: Approximate reciprocal from half floating point value SRC0 and 1647 store it to VDST. Guaranted error below 1ulp.<br /> 1648 Operation:<br /> 1649 <code>VDST = APPROX_RCP(ASHALF(SRC0))</code></p> 1596 1650 <h4>V_RCP_F32</h4> 1597 1651 <p>Opcode VOP1: 42 (0x2a) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br /> … … 1687 1741 if (ASDOUBLE(VDST)==INF) 1688 1742 VDST = MAX_DOUBLE</code></p> 1743 <h4>V_RSQ_F16</h4> 1744 <p>Opcode VOP1: 63 (0x3f) for GCN 1.2<br /> 1745 Opcode VOP3A: 383 (0x17f) for GCN 1.2<br /> 1746 Syntax: V_RSQ_F16 VDST, SRC0<br /> 1747 Description: Approximate reciprocal square root from half floating point value SRC0 and 1748 store it to VDST. If SRC0 is negative value, store NAN to VDST. 1749 This instruction doesn't handle denormalized values regardless FLOAT MODE register setup.<br /> 1750 Operation:<br /> 1751 <code>VDST = APPROX_RSQRT(ASHALF(SRC0))</code></p> 1689 1752 <h4>V_RSQ_F32</h4> 1690 1753 <p>Opcode VOP1: 46 (0x2e) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br /> … … 1732 1795 else if (ISNAN(SF)) 1733 1796 VDST = SRC0</code></p> 1797 <h4>V_SQRT_F16</h4> 1798 <p>Opcode VOP1: 62 (0x3e) for GCN 1.2<br /> 1799 Opcode VOP3A: 382 (0x17e) for GCN 1.2<br /> 1800 Syntax: V_SQRT_F16 VDST, SRC0<br /> 1801 Description: Compute square root of half floating point value SRC0, and 1802 store result to VDST. If SRC0 is negative value then store NaN to VDST.<br /> 1803 Operation:<br /> 1804 <code>if (ASHALF(SRC0)>=0.0) 1805 VDST = APPROX_SQRT(ASHALF(SRC0)) 1806 else 1807 VDST = NAN_H</code></p> 1734 1808 <h4>V_SQRT_F32</h4> 1735 1809 <p>Opcode VOP1: 51 (0x33) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />