Changes between Version 28 and Version 29 of GcnInstrsVop1


Ignore:
Timestamp:
Jun 17, 2017, 10:00:25 AM (2 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVop1

    v28 v29  
    12531253else
    12541254    VDST = (INT32)SF&gt;=0 ? 2147483647 : -2147483648</code></p>
     1255<h4>V_CVT_I16_F16</h4>
     1256<p>Opcode VOP1: 60 (0x3c)<br />
     1257Opcode VOP3A: 380 (0x17c) for GCN 1.2<br />
     1258Syntax: V_CVT_I16_F16 VDST, SRC0<br />
     1259Description: Convert 16-bit floating point value from SRC0 to signed 16-bit integer, and
     1260store result to VDST. Conversion uses rounding to zero. If value is higher/lower than
     1261maximal/minimal integer then store MAX_INT16/MIN_INT16 to VDST.
     1262If input value is NaN then store 0 to VDST.<br />
     1263Operation:<br />
     1264<code>VDST = 0
     1265if (!ISNAN(ASHALF(SRC0)))
     1266    VDST = (INT16)MAX(MIN(RNDTZINT(ASHALF(SRC0)), 32767.0), -32768.0)</code></p>
    12551267<h4>V_CVT_I32_F32</h4>
    12561268<p>Opcode VOP1: 8 (0x8)<br />
     
    12991311else
    13001312    VDST = (INT32)SF&gt;=0 ? 2147483647 : -2147483648</code></p>
     1313<h4>V_CVT_U16_F16</h4>
     1314<p>Opcode VOP1: 59 (0x3b) for GCN 1.2<br />
     1315Opcode VOP3A: 379 (0x17b) for GCN 1.2<br />
     1316Syntax: V_CVT_U16_F16 VDST, SRC0<br />
     1317Description: Convert 32-bit half floating point value from SRC0 to unsigned 16-bit integer,
     1318and store result to VDST. Conversion uses rounding to zero. If value is higher than
     1319maximal integer then store MAX_UINT16 to VDST. If input value is NaN then store 0 to VDST.<br />
     1320Operation:<br />
     1321<code>VDST = 0
     1322if (!ISNAN(ASHALF(SRC0)))
     1323    VDST = (UINT16)MIN(RNDTZINT(ASHALF(SRC0)), 65535.0)</code></p>
    13011324<h4>V_CVT_U32_F32</h4>
    13021325<p>Opcode VOP1: 7 (0x7)<br />
     
    13231346if (!ISNAN(ASDOUBLE(SRC0)))
    13241347    VDST = (UINT32)MIN(RNDTZINT(ASDOUBLE(SRC0)), 4294967295.0)</code></p>
     1348<h4>V_EXP_F16</h4>
     1349<p>Opcode VOP1: 65 (0x41) for GCN 1.2<br />
     1350Opcode VOP3A: 385 (0x181) for GCN 1.2<br />
     1351Syntax: V_EXP_F16 VDST, SRC0<br />
     1352Description: Approximate power of two from half FP value SRC0 and store it to VDST.
     1353Instruction always handles dernomals in output regardless floatmode in MODE register.<br />
     1354Operation:<br />
     1355<code>VDST = APPROX_POW2(ASHALF(SRC0))</code></p>
    13251356<h4>V_EXP_F32</h4>
    13261357<p>Opcode VOP1: 37 (0x25) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2<br />
     
    14961527        VDST = -MAX_FLOAT
    14971528}</code></p>
     1529<h4>V_LOG_F16</h4>
     1530<p>Opcode VOP1: 64 (0x40) for GCN 1.2<br />
     1531Opcode VOP3A: 384 (0x180) for GCN 1.2<br />
     1532Syntax: V_LOG_F16 VDST, SRC0<br />
     1533Description: Approximate logarithm of base 2 from half floating point value SRC0, and store
     1534result to VDST. If SRC0 is negative then store -NaN to VDST.
     1535This instruction handle denormalized values regardless FLOAT MODE register setup.<br />
     1536Operation:<br />
     1537<code>HALF F = ASHALF(SRC0)
     1538if (F==1.0)
     1539    VDST = 0.0h
     1540if (F&lt;0.0)
     1541    VDST = -NaN_F
     1542else
     1543    VDST = APPROX_LOG2(F)</code></p>
    14981544<h4>V_LOG_F32</h4>
    14991545<p>Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
     
    15941640if (ABS(ASDOUBLE(VDST))==INF)
    15951641    VDST = SIGN(ASDOUBLE(VDST)) * MAX_DOUBLE</code></p>
     1642<h4>V_RCP_F16</h4>
     1643<p>Opcode VOP1: 61 (0x3d) for GCN 1.2<br />
     1644Opcode VOP3A: 381 (0x17d) for GCN 1.2<br />
     1645Syntax: V_RCP_F16 VDST, SRC0<br />
     1646Description: Approximate reciprocal from half floating point value SRC0 and
     1647store it to VDST. Guaranted error below 1ulp.<br />
     1648Operation:<br />
     1649<code>VDST = APPROX_RCP(ASHALF(SRC0))</code></p>
    15961650<h4>V_RCP_F32</h4>
    15971651<p>Opcode VOP1: 42 (0x2a) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br />
     
    16871741if (ASDOUBLE(VDST)==INF)
    16881742    VDST = MAX_DOUBLE</code></p>
     1743<h4>V_RSQ_F16</h4>
     1744<p>Opcode VOP1: 63 (0x3f) for GCN 1.2<br />
     1745Opcode VOP3A: 383 (0x17f) for GCN 1.2<br />
     1746Syntax: V_RSQ_F16 VDST, SRC0<br />
     1747Description: Approximate reciprocal square root from half floating point value SRC0 and
     1748store it to VDST. If SRC0 is negative value, store -NAN to VDST.
     1749This instruction doesn't handle denormalized values regardless FLOAT MODE register setup.<br />
     1750Operation:<br />
     1751<code>VDST = APPROX_RSQRT(ASHALF(SRC0))</code></p>
    16891752<h4>V_RSQ_F32</h4>
    16901753<p>Opcode VOP1: 46 (0x2e) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
     
    17321795else if (ISNAN(SF))
    17331796    VDST = SRC0</code></p>
     1797<h4>V_SQRT_F16</h4>
     1798<p>Opcode VOP1: 62 (0x3e) for GCN 1.2<br />
     1799Opcode VOP3A: 382 (0x17e) for GCN 1.2<br />
     1800Syntax: V_SQRT_F16 VDST, SRC0<br />
     1801Description: Compute square root of half floating point value SRC0, and
     1802store result to VDST. If SRC0 is negative value then store -NaN to VDST.<br />
     1803Operation:<br />
     1804<code>if (ASHALF(SRC0)&gt;=0.0)
     1805    VDST = APPROX_SQRT(ASHALF(SRC0))
     1806else
     1807    VDST = -NAN_H</code></p>
    17341808<h4>V_SQRT_F32</h4>
    17351809<p>Opcode VOP1: 51 (0x33) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />