| 1074 | <h4>V_CVT_F32_I32</h4> |
| 1075 | <p>Opcode VOP2: 5 (0x5)<br /> |
| 1076 | Opcode VOP3A: 389 (0x185) for GCN 1.0/1.1; 325 (0x145) for GCN 1.2<br /> |
| 1077 | Syntax: V_CVT_F32_I32 VDST, SRC0<br /> |
| 1078 | Description: Convert signed 32-bit integer to single FP value, and store it to VDST.<br /> |
| 1079 | Operation:<br /> |
| 1080 | <code>VDST = (FLOAT)(INT32)SRC0</code></p> |
| 1081 | <h4>V_CVT_F32_U32</h4> |
| 1082 | <p>Opcode VOP2: 6 (0x6)<br /> |
| 1083 | Opcode VOP3A: 390 (0x186) for GCN 1.0/1.1; 326 (0x146) for GCN 1.2<br /> |
| 1084 | Syntax: V_CVT_F32_U32 VDST, SRC0<br /> |
| 1085 | Description: Convert unsigned 32-bit integer to single FP value, and store it to VDST.<br /> |
| 1086 | Operation:<br /> |
| 1087 | ``` |
| 1088 | VDST = (FLOAT)SRC0</p> |
| 1089 | <h4>V_CVT_F64_I32</h4> |
| 1090 | <p>Opcode VOP2: 4 (0x4)<br /> |
| 1091 | Opcode VOP3A: 388 (0x184) for GCN 1.0/1.1; 324 (0x144) for GCN 1.2<br /> |
| 1092 | Syntax: V_CVT_F64_I32 VDST(2), SRC0<br /> |
| 1093 | Description: Convert signed 32-bit integer to double FP value, and store it to VDST.<br /> |
| 1094 | Operation:<br /> |
| 1095 | <code>VDST = (DOUBLE)(INT32)SRC0</code></p> |
| 1096 | <h4>V_CVT_I32_F32</h4> |
| 1097 | <p>Opcode VOP2: 8 (0x8)<br /> |
| 1098 | Opcode VOP3A: 392 (0x188) for GCN 1.0/1.1; 328 (0x148) for GCN 1.2<br /> |
| 1099 | Syntax: V_CVT_I32_F32 VDST, SRC0<br /> |
| 1100 | Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and |
| 1101 | store result to VDST. Conversion uses rounding to zero. If value is higher/lower than |
| 1102 | maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST. |
| 1103 | If input value is NaN then store 0 to VDST.<br /> |
| 1104 | Operation:<br /> |
| 1105 | <code>VDST = 0 |
| 1106 | if (SRC0!=NAN) |
| 1107 | VDST = (INT32)MAX(MIN(RNDTZINT(ASFLOAT(SRC0)), 2147483647.0), -2147483648.0)</code></p> |
| 1108 | <h4>V_CVT_I32_F64</h4> |
| 1109 | <p>Opcode VOP2: 3 (0x3)<br /> |
| 1110 | Opcode VOP3A: 387 (0x183) for GCN 1.0/1.1; 323 (0x143) for GCN 1.2<br /> |
| 1111 | Syntax: V_CVT_I32_F64 VDST, SRC0(2)<br /> |
| 1112 | Description: Convert 64-bit floating point value from SRC0 to signed 32-bit integer, and |
| 1113 | store result to VDST. Conversion uses rounding to zero. If value is higher/lower than |
| 1114 | maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST. |
| 1115 | If input value is NaN then store 0 to VDST.<br /> |
| 1116 | Operation:<br /> |
| 1117 | <code>VDST = 0 |
| 1118 | if (SRC0!=NAN) |
| 1119 | VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)</code></p> |
| 1120 | <h4>V_CVT_U32_F32</h4> |
| 1121 | <p>Opcode VOP2: 7 (0x7)<br /> |
| 1122 | Opcode VOP3A: 391 (0x187) for GCN 1.0/1.1; 327 (0x147) for GCN 1.2<br /> |
| 1123 | Syntax: V_CVT_U32_F32 VDST, SRC0<br /> |
| 1124 | Description: Convert 32-bit floating point value from SRC0 to unsigned 32-bit integer, and |
| 1125 | store result to VDST. Conversion uses rounding to zero. If value is higher than |
| 1126 | maximal integer then store MAX_UINT32 to VDST. |
| 1127 | If input value is NaN then store 0 to VDST.<br /> |
| 1128 | Operation:<br /> |
| 1129 | <code>VDST = 0 |
| 1130 | if (SRC0!=NAN) |
| 1131 | VDST = (UINT32)MIN(RNDTZINT(ASFLOAT(SRC0)), 4294967295.0)</code></p> |
| 1132 | <h4>V_MOV_B32</h4> |
| 1133 | <p>Opcode VOP2: 1 (0x1)<br /> |
| 1134 | Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br /> |
| 1135 | Syntax: V_MOV_B32 VDST, SRC0<br /> |
| 1136 | Description: Move SRC0 into VDST.<br /> |
| 1137 | Operation:<br /> |
| 1138 | <code>VDST = SRC0</code></p> |
| 1140 | <p>Opcode VOP2: 0 (0x0)<br /> |
| 1141 | Opcode VOP3A: 384 (0x180) for GCN 1.0/1.1; 320 (0x140) for GCN 1.2<br /> |
| 1142 | Syntax: V_NOP<br /> |
| 1143 | Description: Do nothing.</p> |
| 1144 | <h4>V_READFIRSTLANE_B32</h4> |
| 1145 | <p>Opcode VOP2: 2 (0x2)<br /> |
| 1146 | Opcode VOP3A: 386 (0x182) for GCN 1.0/1.1; 322 (0x142) for GCN 1.2<br /> |
| 1147 | Syntax: V_READFIRSTLANE_B32 SDST, VSRC0<br /> |
| 1148 | Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) is first active lane id or |
| 1149 | first lane id all lanes are inactive. SSRC1 can be SGPR or M0. Ignores EXEC mask.<br /> |
| 1150 | Operation:<br /> |
| 1151 | Operation:<br /> |
| 1152 | <code>UINT8 firstlane = 0 |
| 1153 | for (UINT8 i = 0; i < 64; i++) |
| 1154 | if ((1ULL<<i) & EXEC) != 0) |
| 1155 | { firstlane = i; break; } |
| 1156 | SDST = VSRC0[firstlane]</code></p> |