Changes between Version 29 and Version 30 of GcnInstrsVop1
 Timestamp:
 Jun 17, 2017, 11:00:27 AM (20 months ago)
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GcnInstrsVop1
v29 v30 1453 1453 else 1454 1454 VDST = NAN * SIGN(SD)</code></p> 1455 <h4>V_FREXP_EXP_I16_F16</h4> 1456 <p>Opcode VOP1: 67 (0x43) for GCN 1.2<br /> 1457 Opcode VOP3A: 387 (0x183) for GCN 1.2<br /> 1458 Syntax: V_FREXP_EXP_I16_F16 VDST, SRC0<br /> 1459 Description: Get exponent plus 1 from half FP value SRC0, and store that exponent to VDST 1460 as 16bit signed integer. This instruction realizes frexp function. 1461 If SRC0 is infinity or NAN then store 0 to VDST.<br /> 1462 Operation:<br /> 1463 <code>HALF SF = ASHALF(SRC0) 1464 if (ABS(SF) != INF_H && !ISNAN(SF)) 1465 VDST = (INT16)FREXP_EXP(SF) 1466 else 1467 VDST = 0</code></p> 1455 1468 <h4>V_FREXP_EXP_I32_F32</h4> 1456 1469 <p>Opcode VOP1: 63 (0x3f) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2<br /> … … 1459 1472 Description: Get exponent plus 1 from single FP value SRC0, and store that exponent to VDST. 1460 1473 This instruction realizes frexp function. 1461 If SRC0 is infinity or NAN then store 1 to VDST.<br />1474 If SRC0 is infinity or NAN then store 1 if GCN 1.0 or 0 to VDST.<br /> 1462 1475 Operation:<br /> 1463 1476 <code>FLOAT SF = ASFLOAT(SRC0) … … 1465 1478 VDST = FREXP_EXP(SF) 1466 1479 else 1467 VDST = 1</code></p> 1480 VDST = 1 // GCN 1.0 1481 VDST = 0 // later</code></p> 1468 1482 <h4>V_FREXP_EXP_I32_F64</h4> 1469 1483 <p>Opcode VOP1: 60 (0x3c) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2<br /> … … 1472 1486 Description: Get exponent plus 1 from double FP value SRC0, and store that exponent to VDST. 1473 1487 This instruction realizes frexp function. 1474 If SRC0 is infinity or NAN then store 1 to VDST.<br />1488 If SRC0 is infinity or NAN then store 1 if GCN 1.0 or 0 to VDST.<br /> 1475 1489 Operation:<br /> 1476 1490 <code>DOUBLE SD = ASDOUBLE(SRC0) … … 1478 1492 VDST = FREXP_EXP(SD) 1479 1493 else 1480 VDST = 1</code></p> 1494 VDST = 1 // GCN 1.0 1495 VDST = 0 // later</code></p> 1496 <h4>V_FREXP_MANT_F16</h4> 1497 <p>Opcode VOP1: 66 (0x42) for GCN 1.2<br /> 1498 Opcode VOP3A: 386 (0x182) for GCN 1.2<br /> 1499 Syntax: V_FREXP_MANT_F16 VDST, SRC0<br /> 1500 Description: Get mantisa from half FP value SRC0, and store it to VDST. Mantisa includes 1501 sign of input.<br /> 1502 Operation:<br /> 1503 <code>HALF SF = ASHALF(SRC0) 1504 if (ABS(SF) == INF) 1505 VDST = SF 1506 else if (!ISNAN(SF)) 1507 VDST = FREXP_MANT(SF) * SIGN(SF) 1508 else 1509 VDST = NAN_H * SIGN(SF)</code></p> 1481 1510 <h4>V_FREXP_MANT_F32</h4> 1482 1511 <p>Opcode VOP1: 64 (0x40) for GCN 1.0/1.1; 52 (0x34) for GCN 1.2<br /> 1483 1512 Opcode VOP3A: 448 (0x1c0) for GCN 1.0/1.1; 372 (0x174) for GCN 1.2<br /> 1484 1513 Syntax: V_FREXP_MANT_F32 VDST, SRC0<br /> 1485 Description: Get mantisa from double FP value SRC0, and store it to VDST. Mantisa includes1486 sign of input. If SRC0 is infinity then store NAN to VDST.<br />1514 Description: Get mantisa from single FP value SRC0, and store it to VDST. Mantisa includes 1515 sign of input. For GCN 1.0, if SRC0 is infinity then store NAN to VDST.<br /> 1487 1516 Operation:<br /> 1488 1517 <code>FLOAT SF = ASFLOAT(SRC0) 1489 1518 if (ABS(SF) == INF) 1490 VDST = NAN 1519 VDST = NAN // GCN 1.0 1520 VDST = SF // later 1491 1521 else if (!ISNAN(SF)) 1492 1522 VDST = FREXP_MANT(SF) * SIGN(SF) … … 1502 1532 <code>DOUBLE SD = ASDOUBLE(SRC0) 1503 1533 if (ABS(SD) == INF) 1504 VDST = NAN 1534 VDST = NAN // GCN 1.0 1535 VDST = SF // later 1505 1536 else if (!ISNAN(SD)) 1506 1537 VDST = FREXP_MANT(SD) * SIGN(SD)