Changes between Version 32 and Version 33 of GcnInstrsVop1
- Timestamp:
- 11/24/17 23:00:30 (6 years ago)
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GcnInstrsVop1
v32 v33 679 679 </tbody> 680 680 </table> 681 <p>List of the instructions by opcode (GCN 1.2 ):</p>681 <p>List of the instructions by opcode (GCN 1.2/1.4):</p> 682 682 <table> 683 683 <thead> … … 685 685 <th>Opcode</th> 686 686 <th>Opcode(VOP3)</th> 687 <th>Mnemonic</th> 687 <th>Mnemonic (GCN 1.2)</th> 688 <th>Mnemonic (GCN 1.4)</th> 688 689 </tr> 689 690 </thead> … … 693 694 <td>320 (0x140)</td> 694 695 <td>V_NOP</td> 696 <td>V_NOP</td> 695 697 </tr> 696 698 <tr> … … 698 700 <td>321 (0x141)</td> 699 701 <td>V_MOV_B32</td> 702 <td>V_MOV_B32</td> 700 703 </tr> 701 704 <tr> … … 703 706 <td>322 (0x142)</td> 704 707 <td>V_READFIRSTLANE_B32</td> 708 <td>V_READFIRSTLANE_B32</td> 705 709 </tr> 706 710 <tr> … … 708 712 <td>323 (0x143)</td> 709 713 <td>V_CVT_I32_F64</td> 714 <td>V_CVT_I32_F64</td> 710 715 </tr> 711 716 <tr> … … 713 718 <td>324 (0x144)</td> 714 719 <td>V_CVT_F64_I32</td> 720 <td>V_CVT_F64_I32</td> 715 721 </tr> 716 722 <tr> … … 718 724 <td>325 (0x145)</td> 719 725 <td>V_CVT_F32_I32</td> 726 <td>V_CVT_F32_I32</td> 720 727 </tr> 721 728 <tr> … … 723 730 <td>326 (0x146)</td> 724 731 <td>V_CVT_F32_U32</td> 732 <td>V_CVT_F32_U32</td> 725 733 </tr> 726 734 <tr> … … 728 736 <td>327 (0x147)</td> 729 737 <td>V_CVT_U32_F32</td> 738 <td>V_CVT_U32_F32</td> 730 739 </tr> 731 740 <tr> … … 733 742 <td>328 (0x148)</td> 734 743 <td>V_CVT_I32_F32</td> 744 <td>V_CVT_I32_F32</td> 735 745 </tr> 736 746 <tr> … … 738 748 <td>329 (0x149)</td> 739 749 <td>V_MOV_FED_B32</td> 750 <td>V_MOV_FED_B32</td> 740 751 </tr> 741 752 <tr> … … 743 754 <td>330 (0x14a)</td> 744 755 <td>V_CVT_F16_F32</td> 756 <td>V_CVT_F16_F32</td> 745 757 </tr> 746 758 <tr> … … 748 760 <td>331 (0x14b)</td> 749 761 <td>V_CVT_F32_F16</td> 762 <td>V_CVT_F32_F16</td> 750 763 </tr> 751 764 <tr> … … 753 766 <td>332 (0x14c)</td> 754 767 <td>V_CVT_RPI_I32_F32</td> 768 <td>V_CVT_RPI_I32_F32</td> 755 769 </tr> 756 770 <tr> … … 758 772 <td>333 (0x14d)</td> 759 773 <td>V_CVT_FLR_I32_F32</td> 774 <td>V_CVT_FLR_I32_F32</td> 760 775 </tr> 761 776 <tr> … … 763 778 <td>334 (0x14e)</td> 764 779 <td>V_CVT_OFF_F32_I4</td> 780 <td>V_CVT_OFF_F32_I4</td> 765 781 </tr> 766 782 <tr> … … 768 784 <td>335 (0x14f)</td> 769 785 <td>V_CVT_F32_F64</td> 786 <td>V_CVT_F32_F64</td> 770 787 </tr> 771 788 <tr> … … 773 790 <td>336 (0x150)</td> 774 791 <td>V_CVT_F64_F32</td> 792 <td>V_CVT_F64_F32</td> 775 793 </tr> 776 794 <tr> … … 778 796 <td>337 (0x151)</td> 779 797 <td>V_CVT_F32_UBYTE0</td> 798 <td>V_CVT_F32_UBYTE0</td> 780 799 </tr> 781 800 <tr> … … 783 802 <td>338 (0x152)</td> 784 803 <td>V_CVT_F32_UBYTE1</td> 804 <td>V_CVT_F32_UBYTE1</td> 785 805 </tr> 786 806 <tr> … … 788 808 <td>339 (0x153)</td> 789 809 <td>V_CVT_F32_UBYTE2</td> 810 <td>V_CVT_F32_UBYTE2</td> 790 811 </tr> 791 812 <tr> … … 793 814 <td>340 (0x154)</td> 794 815 <td>V_CVT_F32_UBYTE3</td> 816 <td>V_CVT_F32_UBYTE3</td> 795 817 </tr> 796 818 <tr> … … 798 820 <td>341 (0x155)</td> 799 821 <td>V_CVT_U32_F64</td> 822 <td>V_CVT_U32_F64</td> 800 823 </tr> 801 824 <tr> … … 803 826 <td>342 (0x156)</td> 804 827 <td>V_CVT_F64_U32</td> 828 <td>V_CVT_F64_U32</td> 805 829 </tr> 806 830 <tr> … … 808 832 <td>343 (0x157)</td> 809 833 <td>V_TRUNC_F64</td> 834 <td>V_TRUNC_F64</td> 810 835 </tr> 811 836 <tr> … … 813 838 <td>344 (0x158)</td> 814 839 <td>V_CEIL_F64</td> 840 <td>V_CEIL_F64</td> 815 841 </tr> 816 842 <tr> … … 818 844 <td>345 (0x159)</td> 819 845 <td>V_RNDNE_F64</td> 846 <td>V_RNDNE_F64</td> 820 847 </tr> 821 848 <tr> … … 823 850 <td>346 (0x15a)</td> 824 851 <td>V_FLOOR_F64</td> 852 <td>V_FLOOR_F64</td> 825 853 </tr> 826 854 <tr> … … 828 856 <td>347 (0x15b)</td> 829 857 <td>V_FRACT_F32</td> 858 <td>V_FRACT_F32</td> 830 859 </tr> 831 860 <tr> … … 833 862 <td>348 (0x15c)</td> 834 863 <td>V_TRUNC_F32</td> 864 <td>V_TRUNC_F32</td> 835 865 </tr> 836 866 <tr> … … 838 868 <td>349 (0x15d)</td> 839 869 <td>V_CEIL_F32</td> 870 <td>V_CEIL_F32</td> 840 871 </tr> 841 872 <tr> … … 843 874 <td>350 (0x15e)</td> 844 875 <td>V_RNDNE_F32</td> 876 <td>V_RNDNE_F32</td> 845 877 </tr> 846 878 <tr> … … 848 880 <td>351 (0x15f)</td> 849 881 <td>V_FLOOR_F32</td> 882 <td>V_FLOOR_F32</td> 850 883 </tr> 851 884 <tr> … … 853 886 <td>352 (0x160)</td> 854 887 <td>V_EXP_F32</td> 888 <td>V_EXP_F32</td> 855 889 </tr> 856 890 <tr> … … 858 892 <td>353 (0x161)</td> 859 893 <td>V_LOG_F32</td> 894 <td>V_LOG_F32</td> 860 895 </tr> 861 896 <tr> … … 863 898 <td>354 (0x162)</td> 864 899 <td>V_RCP_F32</td> 900 <td>V_RCP_F32</td> 865 901 </tr> 866 902 <tr> … … 868 904 <td>355 (0x163)</td> 869 905 <td>V_RCP_IFLAG_F32</td> 906 <td>V_RCP_IFLAG_F32</td> 870 907 </tr> 871 908 <tr> … … 873 910 <td>356 (0x164)</td> 874 911 <td>V_RSQ_F32</td> 912 <td>V_RSQ_F32</td> 875 913 </tr> 876 914 <tr> … … 878 916 <td>357 (0x165)</td> 879 917 <td>V_RCP_F64</td> 918 <td>V_RCP_F64</td> 880 919 </tr> 881 920 <tr> … … 883 922 <td>358 (0x166)</td> 884 923 <td>V_RSQ_F64</td> 924 <td>V_RSQ_F64</td> 885 925 </tr> 886 926 <tr> … … 888 928 <td>359 (0x167)</td> 889 929 <td>V_SQRT_F32</td> 930 <td>V_SQRT_F32</td> 890 931 </tr> 891 932 <tr> … … 893 934 <td>360 (0x168)</td> 894 935 <td>V_SQRT_F64</td> 936 <td>V_SQRT_F64</td> 895 937 </tr> 896 938 <tr> … … 898 940 <td>361 (0x169)</td> 899 941 <td>V_SIN_F32</td> 942 <td>V_SIN_F32</td> 900 943 </tr> 901 944 <tr> … … 903 946 <td>362 (0x16a)</td> 904 947 <td>V_COS_F32</td> 948 <td>V_COS_F32</td> 905 949 </tr> 906 950 <tr> … … 908 952 <td>363 (0x16b)</td> 909 953 <td>V_NOT_B32</td> 954 <td>V_NOT_B32</td> 910 955 </tr> 911 956 <tr> … … 913 958 <td>364 (0x16c)</td> 914 959 <td>V_BFREV_B32</td> 960 <td>V_BFREV_B32</td> 915 961 </tr> 916 962 <tr> … … 918 964 <td>365 (0x16d)</td> 919 965 <td>V_FFBH_U32</td> 966 <td>V_FFBH_U32</td> 920 967 </tr> 921 968 <tr> … … 923 970 <td>366 (0x16e)</td> 924 971 <td>V_FFBL_B32</td> 972 <td>V_FFBL_B32</td> 925 973 </tr> 926 974 <tr> … … 928 976 <td>367 (0x16f)</td> 929 977 <td>V_FFBH_I32</td> 978 <td>V_FFBH_I32</td> 930 979 </tr> 931 980 <tr> … … 933 982 <td>368 (0x170)</td> 934 983 <td>V_FREXP_EXP_I32_F64</td> 984 <td>V_FREXP_EXP_I32_F64</td> 935 985 </tr> 936 986 <tr> … … 938 988 <td>369 (0x171)</td> 939 989 <td>V_FREXP_MANT_F64</td> 990 <td>V_FREXP_MANT_F64</td> 940 991 </tr> 941 992 <tr> … … 943 994 <td>370 (0x172)</td> 944 995 <td>V_FRACT_F64</td> 996 <td>V_FRACT_F64</td> 945 997 </tr> 946 998 <tr> … … 948 1000 <td>371 (0x173)</td> 949 1001 <td>V_FREXP_EXP_I32_F32</td> 1002 <td>V_FREXP_EXP_I32_F32</td> 950 1003 </tr> 951 1004 <tr> … … 953 1006 <td>372 (0x174)</td> 954 1007 <td>V_FREXP_MANT_F32</td> 1008 <td>V_FREXP_MANT_F32</td> 955 1009 </tr> 956 1010 <tr> … … 958 1012 <td>373 (0x175)</td> 959 1013 <td>V_CLREXCP</td> 1014 <td>V_CLREXCP</td> 960 1015 </tr> 961 1016 <tr> … … 963 1018 <td>374 (0x176)</td> 964 1019 <td>V_MOVRELD_B32</td> 1020 <td>V_MOV_PRSV_B32</td> 965 1021 </tr> 966 1022 <tr> … … 968 1024 <td>375 (0x177)</td> 969 1025 <td>V_MOVRELS_B32</td> 1026 <td>V_SCREEN_PARTITION_4SE_B32</td> 970 1027 </tr> 971 1028 <tr> … … 973 1030 <td>376 (0x178)</td> 974 1031 <td>V_MOVRELSD_B32</td> 1032 <td>--</td> 975 1033 </tr> 976 1034 <tr> … … 978 1036 <td>377 (0x179)</td> 979 1037 <td>V_CVT_F16_U16</td> 1038 <td>V_CVT_F16_U16</td> 980 1039 </tr> 981 1040 <tr> … … 983 1042 <td>378 (0x17a)</td> 984 1043 <td>V_CVT_F16_I16</td> 1044 <td>V_CVT_F16_I16</td> 985 1045 </tr> 986 1046 <tr> … … 988 1048 <td>379 (0x17b)</td> 989 1049 <td>V_CVT_U16_F16</td> 1050 <td>V_CVT_U16_F16</td> 990 1051 </tr> 991 1052 <tr> … … 993 1054 <td>380 (0x17c)</td> 994 1055 <td>V_CVT_I16_F16</td> 1056 <td>V_CVT_I16_F16</td> 995 1057 </tr> 996 1058 <tr> … … 998 1060 <td>381 (0x17d)</td> 999 1061 <td>V_RCP_F16</td> 1062 <td>V_RCP_F16</td> 1000 1063 </tr> 1001 1064 <tr> … … 1003 1066 <td>382 (0x17e)</td> 1004 1067 <td>V_SQRT_F16</td> 1068 <td>V_SQRT_F16</td> 1005 1069 </tr> 1006 1070 <tr> … … 1008 1072 <td>383 (0x17f)</td> 1009 1073 <td>V_RSQ_F16</td> 1074 <td>V_RSQ_F16</td> 1010 1075 </tr> 1011 1076 <tr> … … 1013 1078 <td>384 (0x180)</td> 1014 1079 <td>V_LOG_F16</td> 1080 <td>V_LOG_F16</td> 1015 1081 </tr> 1016 1082 <tr> … … 1018 1084 <td>385 (0x181)</td> 1019 1085 <td>V_EXP_F16</td> 1086 <td>V_EXP_F16</td> 1020 1087 </tr> 1021 1088 <tr> … … 1023 1090 <td>386 (0x182)</td> 1024 1091 <td>V_FREXP_MANT_F16</td> 1092 <td>V_FREXP_MANT_F16</td> 1025 1093 </tr> 1026 1094 <tr> … … 1028 1096 <td>387 (0x183)</td> 1029 1097 <td>V_FREXP_EXP_I16_F16</td> 1098 <td>V_FREXP_EXP_I16_F16</td> 1030 1099 </tr> 1031 1100 <tr> … … 1033 1102 <td>388 (0x184)</td> 1034 1103 <td>V_FLOOR_F16</td> 1104 <td>V_FLOOR_F16</td> 1035 1105 </tr> 1036 1106 <tr> … … 1038 1108 <td>389 (0x185)</td> 1039 1109 <td>V_CEIL_F16</td> 1110 <td>V_CEIL_F16</td> 1040 1111 </tr> 1041 1112 <tr> … … 1043 1114 <td>390 (0x186)</td> 1044 1115 <td>V_TRUNC_F16</td> 1116 <td>V_TRUNC_F16</td> 1045 1117 </tr> 1046 1118 <tr> … … 1048 1120 <td>391 (0x187)</td> 1049 1121 <td>V_RNDNE_F16</td> 1122 <td>V_RNDNE_F16</td> 1050 1123 </tr> 1051 1124 <tr> … … 1053 1126 <td>392 (0x188)</td> 1054 1127 <td>V_FRACT_F16</td> 1128 <td>V_FRACT_F16</td> 1055 1129 </tr> 1056 1130 <tr> … … 1058 1132 <td>393 (0x189)</td> 1059 1133 <td>V_SIN_F16</td> 1134 <td>V_SIN_F16</td> 1060 1135 </tr> 1061 1136 <tr> … … 1063 1138 <td>394 (0x18a)</td> 1064 1139 <td>V_COS_F16</td> 1140 <td>V_COS_F16</td> 1065 1141 </tr> 1066 1142 <tr> … … 1068 1144 <td>395 (0x18b)</td> 1069 1145 <td>V_EXP_LEGACY_F32</td> 1146 <td>V_EXP_LEGACY_F32</td> 1070 1147 </tr> 1071 1148 <tr> … … 1073 1150 <td>396 (0x18c)</td> 1074 1151 <td>V_LOG_LEGACY_F32</td> 1152 <td>V_LOG_LEGACY_F32</td> 1153 </tr> 1154 <tr> 1155 <td>77 (0x4d)</td> 1156 <td>397 (0x18d)</td> 1157 <td>--</td> 1158 <td>V_CVT_NORM_I16_F16</td> 1159 </tr> 1160 <tr> 1161 <td>78 (0x4e)</td> 1162 <td>398 (0x18e)</td> 1163 <td>--</td> 1164 <td>V_CVT_NORM_U16_F16</td> 1165 </tr> 1166 <tr> 1167 <td>79 (0x4f)</td> 1168 <td>399 (0x18f)</td> 1169 <td>--</td> 1170 <td>V_SAT_PK_U8_I16</td> 1171 </tr> 1172 <tr> 1173 <td>80 (0x50)</td> 1174 <td>400 (0x190)</td> 1175 <td>--</td> 1176 <td>V_SWAP_B32</td> 1075 1177 </tr> 1076 1178 </tbody> … … 1318 1420 if (!ISNAN(ASDOUBLE(SRC0))) 1319 1421 VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)</code></p> 1422 <h4>V_CVT_NORM_I16_F16</h4> 1423 <p>Opcode VOP1: 77 (0x4d) for GCN 1.4<br /> 1424 Opcode VOP3A: 397 (0x18d) for GCN 1.4<br /> 1425 Syntax: V_CVT_NORM_I16_F16 VDST, SRC0(2)<br /> 1426 Description: Convert 16-bit floating point value from SRC0 to signed normalized 16-bit value 1427 by multiplying value by 32768.0 and make conversion to 16-bit signed integer, and 1428 store result to VDST. Conversion depends on rounding mode.<br /> 1429 <code>VDST = 0 1430 if (!ISNAN(ASHALF(SRC0))) 1431 VDST = (INT16)(MAX(MIN(RNDINT(ASHALF(SRC0*32768.0)), 32769.0, -32767.0)))</code></p> 1432 <h4>V_CVT_NORM_U16_F16</h4> 1433 <p>Opcode VOP1: 78 (0x4e) for GCN 1.4<br /> 1434 Opcode VOP3A: 398 (0x18e) for GCN 1.4<br /> 1435 Syntax: V_CVT_NORM_U16_F16 VDST, SRC0(2)<br /> 1436 Description: Convert 16-bit floating point value from SRC0 to unsigned normalized 1437 16-bit value by multiplying value by 65535.0 and make conversion to 1438 16-bit unsigned integer, and store result to VDST. Probably rounds to +Infinity.<br /> 1439 <code>VDST = 0 1440 if (!ISNAN(ASHALF(SRC0))) 1441 VDST = (UINT16)(MAX(MIN(RNDINT(ASHALF(SRC0*65535.0)), 65535.0, 0.0)))</code></p> 1320 1442 <h4>V_CVT_OFF_F32_I4</h4> 1321 1443 <p>Opcode VOP1: 14 (0xe)<br /> … … 1852 1974 if (ASFLOAT(VDST)==INF) 1853 1975 VDST = 0.0</code></p> 1976 <h4>V_SAT_PK_U8_I16</h4> 1977 <p>Opcode VOP1: 79 (0x4f) for GCN 1.4<br /> 1978 Opcode VOP3A: 399 (0x18f) for GCN 1.4<br /> 1979 Syntax: V_SAT_PK_U8_I16 VDST, SRC0<br /> 1980 Description: Saturate two packed signed 16-bit values in SRC0 to 8-bit unsigned value 1981 and store they values to VDST in lower 16-bits.<br /> 1982 <code>VDST = MAX(MIN((INT16)(SRC0&0xffff), 255), 0) 1983 VDST |= MAX(MIN((INT16)(SRC0>>16), 255), 0) << 8</code></p> 1854 1984 <h4>V_SIN_F16</h4> 1855 1985 <p>Opcode VOP1: 73 (0x49) for GCN 1.2<br /> … … 1919 2049 else 1920 2050 VDST = -NAN</code></p> 2051 <h4>V_SWAP_B32</h4> 2052 <p>Opcode VOP1: 80 (0x50) for GCN 1.4<br /> 2053 Opcode VOP3A: 400 (0x190) for GCN 1.4<br /> 2054 Syntax: V_SWAP_B32 VDST, SRC0<br /> 2055 Description: Swap SRC0 and VDST.<br /> 2056 <code>UINT32 TMP = VDST 2057 VDST = SRC0 2058 SRC0 = TMP</code></p> 1921 2059 <h4>V_TRUNC_F16</h4> 1922 2060 <p>Opcode VOP1: 70 (0x46) for GCN 1.2<br />