Changes between Version 32 and Version 33 of GcnInstrsVop1


Ignore:
Timestamp:
11/24/17 23:00:30 (6 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GcnInstrsVop1

    v32 v33  
    679679</tbody>
    680680</table>
    681 <p>List of the instructions by opcode (GCN 1.2):</p>
     681<p>List of the instructions by opcode (GCN 1.2/1.4):</p>
    682682<table>
    683683<thead>
     
    685685<th>Opcode</th>
    686686<th>Opcode(VOP3)</th>
    687 <th>Mnemonic</th>
     687<th>Mnemonic (GCN 1.2)</th>
     688<th>Mnemonic (GCN 1.4)</th>
    688689</tr>
    689690</thead>
     
    693694<td>320 (0x140)</td>
    694695<td>V_NOP</td>
     696<td>V_NOP</td>
    695697</tr>
    696698<tr>
     
    698700<td>321 (0x141)</td>
    699701<td>V_MOV_B32</td>
     702<td>V_MOV_B32</td>
    700703</tr>
    701704<tr>
     
    703706<td>322 (0x142)</td>
    704707<td>V_READFIRSTLANE_B32</td>
     708<td>V_READFIRSTLANE_B32</td>
    705709</tr>
    706710<tr>
     
    708712<td>323 (0x143)</td>
    709713<td>V_CVT_I32_F64</td>
     714<td>V_CVT_I32_F64</td>
    710715</tr>
    711716<tr>
     
    713718<td>324 (0x144)</td>
    714719<td>V_CVT_F64_I32</td>
     720<td>V_CVT_F64_I32</td>
    715721</tr>
    716722<tr>
     
    718724<td>325 (0x145)</td>
    719725<td>V_CVT_F32_I32</td>
     726<td>V_CVT_F32_I32</td>
    720727</tr>
    721728<tr>
     
    723730<td>326 (0x146)</td>
    724731<td>V_CVT_F32_U32</td>
     732<td>V_CVT_F32_U32</td>
    725733</tr>
    726734<tr>
     
    728736<td>327 (0x147)</td>
    729737<td>V_CVT_U32_F32</td>
     738<td>V_CVT_U32_F32</td>
    730739</tr>
    731740<tr>
     
    733742<td>328 (0x148)</td>
    734743<td>V_CVT_I32_F32</td>
     744<td>V_CVT_I32_F32</td>
    735745</tr>
    736746<tr>
     
    738748<td>329 (0x149)</td>
    739749<td>V_MOV_FED_B32</td>
     750<td>V_MOV_FED_B32</td>
    740751</tr>
    741752<tr>
     
    743754<td>330 (0x14a)</td>
    744755<td>V_CVT_F16_F32</td>
     756<td>V_CVT_F16_F32</td>
    745757</tr>
    746758<tr>
     
    748760<td>331 (0x14b)</td>
    749761<td>V_CVT_F32_F16</td>
     762<td>V_CVT_F32_F16</td>
    750763</tr>
    751764<tr>
     
    753766<td>332 (0x14c)</td>
    754767<td>V_CVT_RPI_I32_F32</td>
     768<td>V_CVT_RPI_I32_F32</td>
    755769</tr>
    756770<tr>
     
    758772<td>333 (0x14d)</td>
    759773<td>V_CVT_FLR_I32_F32</td>
     774<td>V_CVT_FLR_I32_F32</td>
    760775</tr>
    761776<tr>
     
    763778<td>334 (0x14e)</td>
    764779<td>V_CVT_OFF_F32_I4</td>
     780<td>V_CVT_OFF_F32_I4</td>
    765781</tr>
    766782<tr>
     
    768784<td>335 (0x14f)</td>
    769785<td>V_CVT_F32_F64</td>
     786<td>V_CVT_F32_F64</td>
    770787</tr>
    771788<tr>
     
    773790<td>336 (0x150)</td>
    774791<td>V_CVT_F64_F32</td>
     792<td>V_CVT_F64_F32</td>
    775793</tr>
    776794<tr>
     
    778796<td>337 (0x151)</td>
    779797<td>V_CVT_F32_UBYTE0</td>
     798<td>V_CVT_F32_UBYTE0</td>
    780799</tr>
    781800<tr>
     
    783802<td>338 (0x152)</td>
    784803<td>V_CVT_F32_UBYTE1</td>
     804<td>V_CVT_F32_UBYTE1</td>
    785805</tr>
    786806<tr>
     
    788808<td>339 (0x153)</td>
    789809<td>V_CVT_F32_UBYTE2</td>
     810<td>V_CVT_F32_UBYTE2</td>
    790811</tr>
    791812<tr>
     
    793814<td>340 (0x154)</td>
    794815<td>V_CVT_F32_UBYTE3</td>
     816<td>V_CVT_F32_UBYTE3</td>
    795817</tr>
    796818<tr>
     
    798820<td>341 (0x155)</td>
    799821<td>V_CVT_U32_F64</td>
     822<td>V_CVT_U32_F64</td>
    800823</tr>
    801824<tr>
     
    803826<td>342 (0x156)</td>
    804827<td>V_CVT_F64_U32</td>
     828<td>V_CVT_F64_U32</td>
    805829</tr>
    806830<tr>
     
    808832<td>343 (0x157)</td>
    809833<td>V_TRUNC_F64</td>
     834<td>V_TRUNC_F64</td>
    810835</tr>
    811836<tr>
     
    813838<td>344 (0x158)</td>
    814839<td>V_CEIL_F64</td>
     840<td>V_CEIL_F64</td>
    815841</tr>
    816842<tr>
     
    818844<td>345 (0x159)</td>
    819845<td>V_RNDNE_F64</td>
     846<td>V_RNDNE_F64</td>
    820847</tr>
    821848<tr>
     
    823850<td>346 (0x15a)</td>
    824851<td>V_FLOOR_F64</td>
     852<td>V_FLOOR_F64</td>
    825853</tr>
    826854<tr>
     
    828856<td>347 (0x15b)</td>
    829857<td>V_FRACT_F32</td>
     858<td>V_FRACT_F32</td>
    830859</tr>
    831860<tr>
     
    833862<td>348 (0x15c)</td>
    834863<td>V_TRUNC_F32</td>
     864<td>V_TRUNC_F32</td>
    835865</tr>
    836866<tr>
     
    838868<td>349 (0x15d)</td>
    839869<td>V_CEIL_F32</td>
     870<td>V_CEIL_F32</td>
    840871</tr>
    841872<tr>
     
    843874<td>350 (0x15e)</td>
    844875<td>V_RNDNE_F32</td>
     876<td>V_RNDNE_F32</td>
    845877</tr>
    846878<tr>
     
    848880<td>351 (0x15f)</td>
    849881<td>V_FLOOR_F32</td>
     882<td>V_FLOOR_F32</td>
    850883</tr>
    851884<tr>
     
    853886<td>352 (0x160)</td>
    854887<td>V_EXP_F32</td>
     888<td>V_EXP_F32</td>
    855889</tr>
    856890<tr>
     
    858892<td>353 (0x161)</td>
    859893<td>V_LOG_F32</td>
     894<td>V_LOG_F32</td>
    860895</tr>
    861896<tr>
     
    863898<td>354 (0x162)</td>
    864899<td>V_RCP_F32</td>
     900<td>V_RCP_F32</td>
    865901</tr>
    866902<tr>
     
    868904<td>355 (0x163)</td>
    869905<td>V_RCP_IFLAG_F32</td>
     906<td>V_RCP_IFLAG_F32</td>
    870907</tr>
    871908<tr>
     
    873910<td>356 (0x164)</td>
    874911<td>V_RSQ_F32</td>
     912<td>V_RSQ_F32</td>
    875913</tr>
    876914<tr>
     
    878916<td>357 (0x165)</td>
    879917<td>V_RCP_F64</td>
     918<td>V_RCP_F64</td>
    880919</tr>
    881920<tr>
     
    883922<td>358 (0x166)</td>
    884923<td>V_RSQ_F64</td>
     924<td>V_RSQ_F64</td>
    885925</tr>
    886926<tr>
     
    888928<td>359 (0x167)</td>
    889929<td>V_SQRT_F32</td>
     930<td>V_SQRT_F32</td>
    890931</tr>
    891932<tr>
     
    893934<td>360 (0x168)</td>
    894935<td>V_SQRT_F64</td>
     936<td>V_SQRT_F64</td>
    895937</tr>
    896938<tr>
     
    898940<td>361 (0x169)</td>
    899941<td>V_SIN_F32</td>
     942<td>V_SIN_F32</td>
    900943</tr>
    901944<tr>
     
    903946<td>362 (0x16a)</td>
    904947<td>V_COS_F32</td>
     948<td>V_COS_F32</td>
    905949</tr>
    906950<tr>
     
    908952<td>363 (0x16b)</td>
    909953<td>V_NOT_B32</td>
     954<td>V_NOT_B32</td>
    910955</tr>
    911956<tr>
     
    913958<td>364 (0x16c)</td>
    914959<td>V_BFREV_B32</td>
     960<td>V_BFREV_B32</td>
    915961</tr>
    916962<tr>
     
    918964<td>365 (0x16d)</td>
    919965<td>V_FFBH_U32</td>
     966<td>V_FFBH_U32</td>
    920967</tr>
    921968<tr>
     
    923970<td>366 (0x16e)</td>
    924971<td>V_FFBL_B32</td>
     972<td>V_FFBL_B32</td>
    925973</tr>
    926974<tr>
     
    928976<td>367 (0x16f)</td>
    929977<td>V_FFBH_I32</td>
     978<td>V_FFBH_I32</td>
    930979</tr>
    931980<tr>
     
    933982<td>368 (0x170)</td>
    934983<td>V_FREXP_EXP_I32_F64</td>
     984<td>V_FREXP_EXP_I32_F64</td>
    935985</tr>
    936986<tr>
     
    938988<td>369 (0x171)</td>
    939989<td>V_FREXP_MANT_F64</td>
     990<td>V_FREXP_MANT_F64</td>
    940991</tr>
    941992<tr>
     
    943994<td>370 (0x172)</td>
    944995<td>V_FRACT_F64</td>
     996<td>V_FRACT_F64</td>
    945997</tr>
    946998<tr>
     
    9481000<td>371 (0x173)</td>
    9491001<td>V_FREXP_EXP_I32_F32</td>
     1002<td>V_FREXP_EXP_I32_F32</td>
    9501003</tr>
    9511004<tr>
     
    9531006<td>372 (0x174)</td>
    9541007<td>V_FREXP_MANT_F32</td>
     1008<td>V_FREXP_MANT_F32</td>
    9551009</tr>
    9561010<tr>
     
    9581012<td>373 (0x175)</td>
    9591013<td>V_CLREXCP</td>
     1014<td>V_CLREXCP</td>
    9601015</tr>
    9611016<tr>
     
    9631018<td>374 (0x176)</td>
    9641019<td>V_MOVRELD_B32</td>
     1020<td>V_MOV_PRSV_B32</td>
    9651021</tr>
    9661022<tr>
     
    9681024<td>375 (0x177)</td>
    9691025<td>V_MOVRELS_B32</td>
     1026<td>V_SCREEN_PARTITION_4SE_B32</td>
    9701027</tr>
    9711028<tr>
     
    9731030<td>376 (0x178)</td>
    9741031<td>V_MOVRELSD_B32</td>
     1032<td>--</td>
    9751033</tr>
    9761034<tr>
     
    9781036<td>377 (0x179)</td>
    9791037<td>V_CVT_F16_U16</td>
     1038<td>V_CVT_F16_U16</td>
    9801039</tr>
    9811040<tr>
     
    9831042<td>378 (0x17a)</td>
    9841043<td>V_CVT_F16_I16</td>
     1044<td>V_CVT_F16_I16</td>
    9851045</tr>
    9861046<tr>
     
    9881048<td>379 (0x17b)</td>
    9891049<td>V_CVT_U16_F16</td>
     1050<td>V_CVT_U16_F16</td>
    9901051</tr>
    9911052<tr>
     
    9931054<td>380 (0x17c)</td>
    9941055<td>V_CVT_I16_F16</td>
     1056<td>V_CVT_I16_F16</td>
    9951057</tr>
    9961058<tr>
     
    9981060<td>381 (0x17d)</td>
    9991061<td>V_RCP_F16</td>
     1062<td>V_RCP_F16</td>
    10001063</tr>
    10011064<tr>
     
    10031066<td>382 (0x17e)</td>
    10041067<td>V_SQRT_F16</td>
     1068<td>V_SQRT_F16</td>
    10051069</tr>
    10061070<tr>
     
    10081072<td>383 (0x17f)</td>
    10091073<td>V_RSQ_F16</td>
     1074<td>V_RSQ_F16</td>
    10101075</tr>
    10111076<tr>
     
    10131078<td>384 (0x180)</td>
    10141079<td>V_LOG_F16</td>
     1080<td>V_LOG_F16</td>
    10151081</tr>
    10161082<tr>
     
    10181084<td>385 (0x181)</td>
    10191085<td>V_EXP_F16</td>
     1086<td>V_EXP_F16</td>
    10201087</tr>
    10211088<tr>
     
    10231090<td>386 (0x182)</td>
    10241091<td>V_FREXP_MANT_F16</td>
     1092<td>V_FREXP_MANT_F16</td>
    10251093</tr>
    10261094<tr>
     
    10281096<td>387 (0x183)</td>
    10291097<td>V_FREXP_EXP_I16_F16</td>
     1098<td>V_FREXP_EXP_I16_F16</td>
    10301099</tr>
    10311100<tr>
     
    10331102<td>388 (0x184)</td>
    10341103<td>V_FLOOR_F16</td>
     1104<td>V_FLOOR_F16</td>
    10351105</tr>
    10361106<tr>
     
    10381108<td>389 (0x185)</td>
    10391109<td>V_CEIL_F16</td>
     1110<td>V_CEIL_F16</td>
    10401111</tr>
    10411112<tr>
     
    10431114<td>390 (0x186)</td>
    10441115<td>V_TRUNC_F16</td>
     1116<td>V_TRUNC_F16</td>
    10451117</tr>
    10461118<tr>
     
    10481120<td>391 (0x187)</td>
    10491121<td>V_RNDNE_F16</td>
     1122<td>V_RNDNE_F16</td>
    10501123</tr>
    10511124<tr>
     
    10531126<td>392 (0x188)</td>
    10541127<td>V_FRACT_F16</td>
     1128<td>V_FRACT_F16</td>
    10551129</tr>
    10561130<tr>
     
    10581132<td>393 (0x189)</td>
    10591133<td>V_SIN_F16</td>
     1134<td>V_SIN_F16</td>
    10601135</tr>
    10611136<tr>
     
    10631138<td>394 (0x18a)</td>
    10641139<td>V_COS_F16</td>
     1140<td>V_COS_F16</td>
    10651141</tr>
    10661142<tr>
     
    10681144<td>395 (0x18b)</td>
    10691145<td>V_EXP_LEGACY_F32</td>
     1146<td>V_EXP_LEGACY_F32</td>
    10701147</tr>
    10711148<tr>
     
    10731150<td>396 (0x18c)</td>
    10741151<td>V_LOG_LEGACY_F32</td>
     1152<td>V_LOG_LEGACY_F32</td>
     1153</tr>
     1154<tr>
     1155<td>77 (0x4d)</td>
     1156<td>397 (0x18d)</td>
     1157<td>--</td>
     1158<td>V_CVT_NORM_I16_F16</td>
     1159</tr>
     1160<tr>
     1161<td>78 (0x4e)</td>
     1162<td>398 (0x18e)</td>
     1163<td>--</td>
     1164<td>V_CVT_NORM_U16_F16</td>
     1165</tr>
     1166<tr>
     1167<td>79 (0x4f)</td>
     1168<td>399 (0x18f)</td>
     1169<td>--</td>
     1170<td>V_SAT_PK_U8_I16</td>
     1171</tr>
     1172<tr>
     1173<td>80 (0x50)</td>
     1174<td>400 (0x190)</td>
     1175<td>--</td>
     1176<td>V_SWAP_B32</td>
    10751177</tr>
    10761178</tbody>
     
    13181420if (!ISNAN(ASDOUBLE(SRC0)))
    13191421    VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)</code></p>
     1422<h4>V_CVT_NORM_I16_F16</h4>
     1423<p>Opcode VOP1: 77 (0x4d) for GCN 1.4<br />
     1424Opcode VOP3A: 397 (0x18d) for GCN 1.4<br />
     1425Syntax: V_CVT_NORM_I16_F16 VDST, SRC0(2)<br />
     1426Description: Convert 16-bit floating point value from SRC0 to signed normalized 16-bit value
     1427by multiplying value by 32768.0 and make conversion to 16-bit signed integer, and
     1428store result to VDST. Conversion depends on rounding mode.<br />
     1429<code>VDST = 0
     1430if (!ISNAN(ASHALF(SRC0)))
     1431    VDST = (INT16)(MAX(MIN(RNDINT(ASHALF(SRC0*32768.0)), 32769.0, -32767.0)))</code></p>
     1432<h4>V_CVT_NORM_U16_F16</h4>
     1433<p>Opcode VOP1: 78 (0x4e) for GCN 1.4<br />
     1434Opcode VOP3A: 398 (0x18e) for GCN 1.4<br />
     1435Syntax: V_CVT_NORM_U16_F16 VDST, SRC0(2)<br />
     1436Description: Convert 16-bit floating point value from SRC0 to unsigned normalized
     143716-bit value by multiplying value by 65535.0 and make conversion to
     143816-bit unsigned integer, and store result to VDST. Probably rounds to +Infinity.<br />
     1439<code>VDST = 0
     1440if (!ISNAN(ASHALF(SRC0)))
     1441    VDST = (UINT16)(MAX(MIN(RNDINT(ASHALF(SRC0*65535.0)), 65535.0, 0.0)))</code></p>
    13201442<h4>V_CVT_OFF_F32_I4</h4>
    13211443<p>Opcode VOP1: 14 (0xe)<br />
     
    18521974if (ASFLOAT(VDST)==INF)
    18531975    VDST = 0.0</code></p>
     1976<h4>V_SAT_PK_U8_I16</h4>
     1977<p>Opcode VOP1: 79 (0x4f) for GCN 1.4<br />
     1978Opcode VOP3A: 399 (0x18f) for GCN 1.4<br />
     1979Syntax: V_SAT_PK_U8_I16 VDST, SRC0<br />
     1980Description: Saturate two packed signed 16-bit values in SRC0 to 8-bit unsigned value
     1981and store they values to VDST in lower 16-bits.<br />
     1982<code>VDST = MAX(MIN((INT16)(SRC0&amp;0xffff), 255), 0)
     1983VDST |= MAX(MIN((INT16)(SRC0&gt;&gt;16), 255), 0) &lt;&lt; 8</code></p>
    18541984<h4>V_SIN_F16</h4>
    18551985<p>Opcode VOP1: 73 (0x49) for GCN 1.2<br />
     
    19192049else
    19202050    VDST = -NAN</code></p>
     2051<h4>V_SWAP_B32</h4>
     2052<p>Opcode VOP1: 80 (0x50) for GCN 1.4<br />
     2053Opcode VOP3A: 400 (0x190) for GCN 1.4<br />
     2054Syntax: V_SWAP_B32 VDST, SRC0<br />
     2055Description: Swap SRC0 and VDST.<br />
     2056<code>UINT32 TMP = VDST
     2057VDST = SRC0
     2058SRC0 = TMP</code></p>
    19212059<h4>V_TRUNC_F16</h4>
    19222060<p>Opcode VOP1: 70 (0x46) for GCN 1.2<br />