Changes between Version 3 and Version 4 of GcnInstrsVop1


Ignore:
Timestamp:
Nov 27, 2015, 11:00:21 PM (5 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GcnInstrsVop1

    v3 v4  
    10721072<h3>Instruction set</h3>
    10731073<p>Alphabetically sorted instruction list:</p>
     1074<h4>V_CVT_F16_F32</h4>
     1075<p>Opcode VOP2: 10 (0xa)<br />
     1076Opcode VOP3A: 394 (0x18a) for GCN 1.0/1.1; 330 (0x14a) for GCN 1.2<br />
     1077Syntax: V_CVT_F16_F32 VDST, SRC0<br />
     1078Description: Convert single FP value to half floating point value with rounding from
     1079MODE register (single FP rounding mode), and store result to VDST.
     1080If absolute value is too high, then store -/+infinity to VDST.<br />
     1081Operation:<br />
     1082<code>VDST = RNDHALF(ASFLOAT(SRC0))</code></p>
     1083<h4>V_CVT_F32_F16</h4>
     1084<p>Opcode VOP2: 11 (0xb)<br />
     1085Opcode VOP3A: 395 (0x18b) for GCN 1.0/1.1; 331 (0x14b) for GCN 1.2<br />
     1086Syntax: V_CVT_F32_F16 VDST, SRC0<br />
     1087Description: Convert half FP value to single FP value, and store result to VDST.<br />
     1088Operation:<br />
     1089<code>VDST = (FLOAT)(ASHALF(SRC0))</code></p>
    10741090<h4>V_CVT_F32_I32</h4>
    10751091<p>Opcode VOP2: 5 (0x5)<br />
     
    11301146if (SRC0!=NAN)
    11311147    VDST = (UINT32)MIN(RNDTZINT(ASFLOAT(SRC0)), 4294967295.0)</code></p>
     1148<h4>V_MOV_FED_B32</h4>
     1149<p>Opcode VOP2: 9 (0x9)<br />
     1150Opcode VOP3A: 393 (0x189) for GCN 1.0/1.1; 329 (0x149) for GCN 1.2<br />
     1151Syntax: V_MOV_FED_B32 VDST, SRC0<br />
     1152Description: Introduce edc double error upon write to dest vgpr without causing an exception
     1153(???).</p>
    11321154<h4>V_MOV_B32</h4>
    11331155<p>Opcode VOP2: 1 (0x1)<br />