Changes between Version 3 and Version 4 of GcnInstrsVop1
- Timestamp:
- 11/27/15 23:00:21 (8 years ago)
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GcnInstrsVop1
v3 v4 1072 1072 <h3>Instruction set</h3> 1073 1073 <p>Alphabetically sorted instruction list:</p> 1074 <h4>V_CVT_F16_F32</h4> 1075 <p>Opcode VOP2: 10 (0xa)<br /> 1076 Opcode VOP3A: 394 (0x18a) for GCN 1.0/1.1; 330 (0x14a) for GCN 1.2<br /> 1077 Syntax: V_CVT_F16_F32 VDST, SRC0<br /> 1078 Description: Convert single FP value to half floating point value with rounding from 1079 MODE register (single FP rounding mode), and store result to VDST. 1080 If absolute value is too high, then store -/+infinity to VDST.<br /> 1081 Operation:<br /> 1082 <code>VDST = RNDHALF(ASFLOAT(SRC0))</code></p> 1083 <h4>V_CVT_F32_F16</h4> 1084 <p>Opcode VOP2: 11 (0xb)<br /> 1085 Opcode VOP3A: 395 (0x18b) for GCN 1.0/1.1; 331 (0x14b) for GCN 1.2<br /> 1086 Syntax: V_CVT_F32_F16 VDST, SRC0<br /> 1087 Description: Convert half FP value to single FP value, and store result to VDST.<br /> 1088 Operation:<br /> 1089 <code>VDST = (FLOAT)(ASHALF(SRC0))</code></p> 1074 1090 <h4>V_CVT_F32_I32</h4> 1075 1091 <p>Opcode VOP2: 5 (0x5)<br /> … … 1130 1146 if (SRC0!=NAN) 1131 1147 VDST = (UINT32)MIN(RNDTZINT(ASFLOAT(SRC0)), 4294967295.0)</code></p> 1148 <h4>V_MOV_FED_B32</h4> 1149 <p>Opcode VOP2: 9 (0x9)<br /> 1150 Opcode VOP3A: 393 (0x189) for GCN 1.0/1.1; 329 (0x149) for GCN 1.2<br /> 1151 Syntax: V_MOV_FED_B32 VDST, SRC0<br /> 1152 Description: Introduce edc double error upon write to dest vgpr without causing an exception 1153 (???).</p> 1132 1154 <h4>V_MOV_B32</h4> 1133 1155 <p>Opcode VOP2: 1 (0x1)<br />