Changes between Initial Version and Version 1 of GcnInstrsVop2


Ignore:
Timestamp:
11/20/15 01:00:14 (8 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • GcnInstrsVop2

    v1 v1  
     1[wiki:ClrxToc Back to Table of content]
     2{{{
     3#!html
     4<h2>GCN ISA VOP2/VOP3 instructions</h2>
     5<p>VOP2 instructions can be encoded in the VOP2 encoding and the VOP3a/VOP3b encoding.
     6List of fields for VOP2 encoding:</p>
     7<table>
     8<thead>
     9<tr>
     10<th>Bits</th>
     11<th>Name</th>
     12<th>Description</th>
     13</tr>
     14</thead>
     15<tbody>
     16<tr>
     17<td>0-8</td>
     18<td>SRC0</td>
     19<td>First (scalar or vector) source operand</td>
     20</tr>
     21<tr>
     22<td>9-16</td>
     23<td>VSRC1</td>
     24<td>Second vector source operand</td>
     25</tr>
     26<tr>
     27<td>17-24</td>
     28<td>VDST</td>
     29<td>Destination vector operand</td>
     30</tr>
     31<tr>
     32<td>25-30</td>
     33<td>OPCODE</td>
     34<td>Operation code</td>
     35</tr>
     36<tr>
     37<td>31</td>
     38<td>ENCODING</td>
     39<td>Encoding type. Must be 0</td>
     40</tr>
     41</tbody>
     42</table>
     43<p>Syntax: INSTRUCTION VDST, SRC0, VSRC1</p>
     44<p>List of fields for VOP3A/VOP3B encoding (GCN 1.0/1.1):</p>
     45<table>
     46<thead>
     47<tr>
     48<th>Bits</th>
     49<th>Name</th>
     50<th>Description</th>
     51</tr>
     52</thead>
     53<tbody>
     54<tr>
     55<td>0-7</td>
     56<td>VDST</td>
     57<td>Vector destination operand</td>
     58</tr>
     59<tr>
     60<td>8-10</td>
     61<td>ABS</td>
     62<td>Absolute modifiers for source operands (VOP3A)</td>
     63</tr>
     64<tr>
     65<td>8-14</td>
     66<td>SDST</td>
     67<td>Scalar destination operand (VOP3B)</td>
     68</tr>
     69<tr>
     70<td>11</td>
     71<td>CLAMP</td>
     72<td>CLAMP modifier (VOP3A)</td>
     73</tr>
     74<tr>
     75<td>15</td>
     76<td>CLAMP</td>
     77<td>CLAMP modifier (VOP3B)</td>
     78</tr>
     79<tr>
     80<td>17-25</td>
     81<td>OPCODE</td>
     82<td>Operation code</td>
     83</tr>
     84<tr>
     85<td>26-31</td>
     86<td>ENCODING</td>
     87<td>Encoding type. Must be 0b110100</td>
     88</tr>
     89<tr>
     90<td>32-40</td>
     91<td>SRC0</td>
     92<td>First (scalar or vector) source operand</td>
     93</tr>
     94<tr>
     95<td>41-49</td>
     96<td>SRC1</td>
     97<td>Second (scalar or vector) source operand</td>
     98</tr>
     99<tr>
     100<td>50-58</td>
     101<td>SRC2</td>
     102<td>Third (scalar or vector) source operand</td>
     103</tr>
     104<tr>
     105<td>59-60</td>
     106<td>OMOD</td>
     107<td>OMOD modifier. Multiplication modifier</td>
     108</tr>
     109<tr>
     110<td>61-63</td>
     111<td>NEG</td>
     112<td>Negation modifier for source operands</td>
     113</tr>
     114</tbody>
     115</table>
     116<p>List of fields for VOP3A encoding (GCN 1.2):</p>
     117<table>
     118<thead>
     119<tr>
     120<th>Bits</th>
     121<th>Name</th>
     122<th>Description</th>
     123</tr>
     124</thead>
     125<tbody>
     126<tr>
     127<td>0-7</td>
     128<td>VDST</td>
     129<td>Destination vector operand</td>
     130</tr>
     131<tr>
     132<td>8-10</td>
     133<td>ABS</td>
     134<td>Absolute modifiers for source operands (VOP3A)</td>
     135</tr>
     136<tr>
     137<td>8-14</td>
     138<td>SDST</td>
     139<td>Scalar destination operand (VOP3B)</td>
     140</tr>
     141<tr>
     142<td>15</td>
     143<td>CLAMP</td>
     144<td>CLAMP modifier</td>
     145</tr>
     146<tr>
     147<td>16-25</td>
     148<td>OPCODE</td>
     149<td>Operation code</td>
     150</tr>
     151<tr>
     152<td>26-31</td>
     153<td>ENCODING</td>
     154<td>Encoding type. Must be 0b110100</td>
     155</tr>
     156<tr>
     157<td>32-40</td>
     158<td>SRC0</td>
     159<td>First (scalar or vector) source operand</td>
     160</tr>
     161<tr>
     162<td>41-49</td>
     163<td>SRC1</td>
     164<td>Second (scalar or vector) source operand</td>
     165</tr>
     166<tr>
     167<td>50-58</td>
     168<td>SRC2</td>
     169<td>Third (scalar or vector) source operand</td>
     170</tr>
     171<tr>
     172<td>59-60</td>
     173<td>OMOD</td>
     174<td>OMOD modifier. Multiplication modifier</td>
     175</tr>
     176<tr>
     177<td>61-63</td>
     178<td>NEG</td>
     179<td>Negation modifier for source operands</td>
     180</tr>
     181</tbody>
     182</table>
     183<p>Syntax: INSTRUCTION VDST, SRC0, SRC1 [MODIFIERS]</p>
     184<p>Modifiers:</p>
     185<ul>
     186<li>CLAMP - clamps destination floating point value in range 0.0-1.0</li>
     187<li>MUL:2, MUL:4, DIV:2 - OMOD modifiers. Multiply destination floating point value by
     1882.0, 4.0 or 0.5 respectively</li>
     189<li>-SRC - negate floating point value from source operand</li>
     190<li>ABS(SRC) - apply absolute value to source operand</li>
     191</ul>
     192<p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and
     193OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p>
     194<p>VOP2 opcodes (0-63) are reflected in VOP3 in range: 256-319.
     195List of the instructions by opcode:</p>
     196<table>
     197<thead>
     198<tr>
     199<th>Opcode</th>
     200<th>Mnemonic (GCN1.0/1.1)</th>
     201<th>Mnemonic (GCN 1.2)</th>
     202</tr>
     203</thead>
     204<tbody>
     205<tr>
     206<td>1 (0x1)</td>
     207<td>--</td>
     208<td>V_ADD_F32</td>
     209</tr>
     210<tr>
     211<td>2 (0x2)</td>
     212<td>--</td>
     213<td>V_SUB_F32</td>
     214</tr>
     215<tr>
     216<td>3 (0x3)</td>
     217<td>V_ADD_F32</td>
     218<td>V_SUBREV_F32</td>
     219</tr>
     220<tr>
     221<td>4 (0x4)</td>
     222<td>V_SUB_F32</td>
     223<td>V_MUL_LEGACY_F32</td>
     224</tr>
     225<tr>
     226<td>5 (0x5)</td>
     227<td>V_SUBREV_F32</td>
     228<td>V_MUL_F32</td>
     229</tr>
     230<tr>
     231<td>6 (0x6)</td>
     232<td>V_MAC_LEGACY_F32</td>
     233<td>V_MUL_I32_I24</td>
     234</tr>
     235<tr>
     236<td>7 (0x7)</td>
     237<td>V_MUL_LEGACY_F32</td>
     238<td>V_MUL_HI_I32_I24</td>
     239</tr>
     240<tr>
     241<td>8 (0x8)</td>
     242<td>V_MUL_F32</td>
     243<td>V_MUL_U32_U24</td>
     244</tr>
     245<tr>
     246<td>9 (0x9)</td>
     247<td>V_MUL_I32_I24</td>
     248<td>V_MUL_HI_U32_U24</td>
     249</tr>
     250<tr>
     251<td>10 (0xa)</td>
     252<td>V_MUL_HI_I32_I24</td>
     253<td>V_MIN_F32</td>
     254</tr>
     255<tr>
     256<td>11 (0xb)</td>
     257<td>V_MUL_U32_U24</td>
     258<td>V_MAX_F32</td>
     259</tr>
     260<tr>
     261<td>12 (0xc)</td>
     262<td>V_MUL_HI_U32_U24</td>
     263<td>V_MIN_I32</td>
     264</tr>
     265<tr>
     266<td>13 (0xd)</td>
     267<td>V_MIN_LEGACY_F32</td>
     268<td>V_MAX_I32</td>
     269</tr>
     270<tr>
     271<td>14 (0xe)</td>
     272<td>V_MAX_LEGACY_F32</td>
     273<td>V_MIN_U32</td>
     274</tr>
     275<tr>
     276<td>15 (0xf)</td>
     277<td>V_MIN_F32</td>
     278<td>V_MAX_U32</td>
     279</tr>
     280</tbody>
     281</table>
     282<h3>Instruction set</h3>
     283<p>Alphabetically sorted instruction list:</p>
     284}}}