Changes between Version 10 and Version 11 of GcnInstrsVop2
- Timestamp:
- 11/22/15 22:00:17 (8 years ago)
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GcnInstrsVop2
v10 v11 567 567 Opcode: VOP3a: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2<br /> 568 568 Syntax: V_AND_B32 VDST, SRC0, SRC1<br /> 569 Description: Do bitwise AND on SRC0 and SRC1 andstore result to VDST.569 Description: Do bitwise AND on SRC0 and SRC1, store result to VDST. 570 570 CLAMP and OMOD modifier doesn't affect on result.<br /> 571 571 Operation:<br /> … … 873 873 Operation:<br /> 874 874 <code>VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1)</code></p> 875 <h4>V_MUL_HI_I32_ 24</h4>875 <h4>V_MUL_HI_I32_I24</h4> 876 876 <p>Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2<br /> 877 877 Opcode VOP3a: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2<br /> 878 Syntax: V_MUL_HI_I32_ 24 VDST, SRC0, SRC1<br />878 Syntax: V_MUL_HI_I32_I24 VDST, SRC0, SRC1<br /> 879 879 Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1 880 880 and store higher 16-bit of the result to VDST with sign extension. … … 915 915 Opcode: VOP3a: 284 (0x11c) for GCN 1.0/1.1; 276 (0x114) for GCN 1.2<br /> 916 916 Syntax: V_OR_B32 VDST, SRC0, SRC1<br /> 917 Description: Do bitwise OR operation on SRC0 and SRC1 andstore result to VDST.917 Description: Do bitwise OR operation on SRC0 and SRC1, store result to VDST. 918 918 CLAMP and OMOD modifier doesn't affect on result.<br /> 919 919 Operation:<br /> … … 963 963 VDST = temp 964 964 SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0)</code></p> 965 <h4>V_SUBREV_F32</h4>966 <p>Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2<br />967 Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2<br />968 Syntax: V_SUBREV_F32 VDST, SRC0, SRC1<br />969 Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST.<br />970 Operation:<br />971 <code>VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0)</code></p>972 965 <h4>V_SUBBREV_U32</h4> 973 966 <p>Opcode VOP2: 42 (0x2a) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br /> … … 985 978 VDST = temp 986 979 SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0)</code></p> 980 <h4>V_SUBREV_F32</h4> 981 <p>Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2<br /> 982 Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2<br /> 983 Syntax: V_SUBREV_F32 VDST, SRC0, SRC1<br /> 984 Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST.<br /> 985 Operation:<br /> 986 <code>VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0)</code></p> 987 987 <h4>V_SUBREV_I32, V_SUBREV_U32</h4> 988 988 <p>Opcode VOP2: 39 (0x27) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2<br /> … … 1002 1002 <p>Opcode: VOP2: 29 (0x1d) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br /> 1003 1003 Opcode: VOP3a: 285 (0x11d) for GCN 1.0/1.1; 277 (0x115) for GCN 1.2<br /> 1004 Syntax: V_ OR_B32 VDST, SRC0, SRC1<br />1005 Description: Do bitwise XOR operation on SRC0 and SRC1 andstore result to VDST.1004 Syntax: V_XOR_B32 VDST, SRC0, SRC1<br /> 1005 Description: Do bitwise XOR operation on SRC0 and SRC1, store result to VDST. 1006 1006 CLAMP and OMOD modifier doesn't affect on result.<br /> 1007 1007 Operation:<br />