Changes between Version 11 and Version 12 of GcnInstrsVop2


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Timestamp:
Nov 22, 2015, 11:00:21 PM (5 years ago)
Author:
trac
Comment:

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  • GcnInstrsVop2

    v11 v12  
    33#!html
    44<h2>GCN ISA VOP2/VOP3 instructions</h2>
    5 <p>VOP2 instructions can be encoded in the VOP2 encoding and the VOP3a/VOP3b encoding.
     5<p>VOP2 instructions can be encoded in the VOP2 encoding and the VOP3A/VOP3B encoding.
    66List of fields for VOP2 encoding:</p>
    77<table>
     
    114114</tbody>
    115115</table>
    116 <p>List of fields for VOP3A encoding (GCN 1.2):</p>
     116<p>List of fields for VOP3A/VOP3B encoding (GCN 1.2):</p>
    117117<table>
    118118<thead>
     
    530530<h4>V_ADD_F32</h4>
    531531<p>Opcode VOP2: 3 (0x3) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2<br />
    532 Opcode VOP3a: 259 (0x103) for GCN 1.0/1.1; 257 (0x101) for GCN 1.2<br />
     532Opcode VOP3A: 259 (0x103) for GCN 1.0/1.1; 257 (0x101) for GCN 1.2<br />
    533533Syntax: V_ADD_F32 VDST, SRC0, SRC1<br />
    534534Description: Add two FP value from SRC0 and SRC1 and store result to VDST.<br />
     
    537537<h4>V_ADD_I32, V_ADD_U32</h4>
    538538<p>Opcode VOP2: 37 (0x25) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2<br />
    539 Opcode VOP3b: 293 (0x125) for GCN 1.0/1.1; 281 (0x119) for GCN 1.2<br />
     539Opcode VOP3B: 293 (0x125) for GCN 1.0/1.1; 281 (0x119) for GCN 1.2<br />
    540540Syntax VOP2 GCN 1.0/1.1: V_ADD_I32 VDST, VCC, SRC0, SRC1<br />
    541 Syntax VOP3b GCN 1.0/1.1: V_ADD_I32 VDST, SDST(2), SRC0, SRC1<br />
     541Syntax VOP3B GCN 1.0/1.1: V_ADD_I32 VDST, SDST(2), SRC0, SRC1<br />
    542542Syntax VOP2 GCN 1.2: V_ADD_U32 VDST, VCC, SRC0, SRC1<br />
    543 Syntax VOP3b GCN 1.2: V_ADD_U32 VDST, SDST(2), SRC0, SRC1<br />
     543Syntax VOP3B GCN 1.2: V_ADD_U32 VDST, SDST(2), SRC0, SRC1<br />
    544544Description: Add SRC0 to SRC1 and store result to VDST and store carry flag to
    545545SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit.<br />
     
    551551<h4>V_ADDC_U32</h4>
    552552<p>Opcode VOP2: 40 (0x28) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />
    553 Opcode VOP3b: 296 (0x128) for GCN 1.0/1.1; 284 (0x11c) for GCN 1.2<br />
     553Opcode VOP3B: 296 (0x128) for GCN 1.0/1.1; 284 (0x11c) for GCN 1.2<br />
    554554Syntax VOP2 GCN 1.0/1.1: V_ADDC_U32 VDST, VCC, SRC0, SRC1, VCC<br />
    555 Syntax VOP3b GCN 1.2: V_ADDC_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
     555Syntax VOP3B GCN 1.2: V_ADDC_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
    556556Description: Add SRC0 to SRC1 with carry stored in SSRC2 bit with number that equal lane id,
    557557and store result to VDST and store carry flag to SDST (or VCC) bit with number
     
    565565<h4>V_AND_B32</h4>
    566566<p>Opcode: VOP2: 27 (0x1b) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2<br />
    567 Opcode: VOP3a: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2<br />
     567Opcode: VOP3A: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2<br />
    568568Syntax: V_AND_B32 VDST, SRC0, SRC1<br />
    569569Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.
     
    573573<h4>V_ASHR_I32</h4>
    574574<p>Opcode VOP2: 23 (0x17) for GCN 1.0/1.1<br />
    575 Opcode VOP3a: 279 (0x117) for GCN 1.0/1.1<br />
     575Opcode VOP3A: 279 (0x117) for GCN 1.0/1.1<br />
    576576Syntax: V_ASHR_I32 VDST, SRC0, SRC1<br />
    577577Description: Arithmetic shift right SRC0 by (SRC1&amp;31) bits and store result into VDST.<br />
     
    580580<h4>V_ASHRREV_I32</h4>
    581581<p>Opcode VOP2: 24 (0x18) for GCN 1.0/1.1; 16 (0x11) for GCN 1.2<br />
    582 Opcode VOP3a: 280 (0x118) for GCN 1.0/1.1; 272 (0x111) for GCN 1.2<br />
     582Opcode VOP3A: 280 (0x118) for GCN 1.0/1.1; 272 (0x111) for GCN 1.2<br />
    583583Syntax: V_ASHRREV_I32 VDST, SRC0, SRC1<br />
    584584Description: Arithmetic shift right SRC1 by (SRC0&amp;31) bits and store result into VDST.<br />
     
    587587<h4>V_BCNT_U32_B32</h4>
    588588<p>Opcode VOP2: 34 (0x22) for GCN 1.0/1.1<br />
    589 Opcode VOP3a: 290 (0x122) for GCN 1.0/1.1<br />
     589Opcode VOP3A: 290 (0x122) for GCN 1.0/1.1<br />
    590590Syntax: V_BCNT_U32_B32 VDST, SRC0, SRC1<br />
    591591Description: Count bits in SRC0, adds SSRC1, and store result to VDST.<br />
     
    594594<h4>V_BFM_B32</h4>
    595595<p>Opcode VOP2: 30 (0x1e) for GCN 1.0/1.1<br />
    596 Opcode VOP3a: 286 (0x11e) for GCN 1.0/1.1<br />
     596Opcode VOP3A: 286 (0x11e) for GCN 1.0/1.1<br />
    597597Syntax: V_BFM_B32 VDST, SRC0, SRC1<br />
    598598Description: Make 32-bit bitmask from (SRC1 &amp; 31) bit that have length (SRC0 &amp; 31) and
     
    602602<h4>V_CNDMASK_B32</h4>
    603603<p>Opcode VOP2: 0 (0x0) for GCN 1.0/1.1; 1 (0x0) for GCN 1.2<br />
    604 Opcode VOP3a: 256 (0x100) for GCN 1.0/1.1; 256 (0x100) for GCN 1.2<br />
     604Opcode VOP3A: 256 (0x100) for GCN 1.0/1.1; 256 (0x100) for GCN 1.2<br />
    605605Syntax VOP2: V_CNDMASK_B32 VDST, SRC0, SRC1, VCC<br />
    606 Syntax VOP3a: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2)<br />
     606Syntax VOP3A: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2)<br />
    607607Description: If bit for current lane of VCC or SDST is set then store SRC1 to VDST,
    608608otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.<br />
     
    611611<h4>V_CVT_PKACCUM_U8_F32</h4>
    612612<p>Opcode VOP2: 44 (0x2c) for GCN 1.0/1.1<br />
    613 Opcode VOP3a: 300 (0x12c) for GCN 1.0/1.1<br />
     613Opcode VOP3A: 300 (0x12c) for GCN 1.0/1.1<br />
    614614Syntax: V_CVT_PKACCUM_U8_F32 VDST, SRC0, SRC1<br />
    615615Description: Convert floating point value from SRC0 to unsigned byte value with
     
    629629<h4>V_CVT_PKNORM_I16_F32</h4>
    630630<p>Opcode VOP2: 45 (0x2d) for GCN 1.0/1.1<br />
    631 Opcode VOP3a: 301 (0x12d) for GCN 1.0/1.1<br />
     631Opcode VOP3A: 301 (0x12d) for GCN 1.0/1.1<br />
    632632Syntax: V_CVT_PKNORM_I16_F32 VDST, SRC0, SRC1<br />
    633633Description: Convert normalized FP value from SRC0 and SRC1 to signed 16-bit integers with
     
    649649<h4>V_CVT_PKNORM_U16_F32</h4>
    650650<p>Opcode VOP2: 46 (0x2e) for GCN 1.0/1.1<br />
    651 Opcode VOP3a: 302 (0x12e) for GCN 1.0/1.1<br />
     651Opcode VOP3A: 302 (0x12e) for GCN 1.0/1.1<br />
    652652Syntax: V_CVT_PKNORM_U16_F32 VDST, SRC0, SRC1<br />
    653653Description: Convert normalized FP value from SRC0 and SRC1 to unsigned 16-bit integers with
     
    668668<h4>V_CVT_PKRTZ_F16_F32</h4>
    669669<p>Opcode VOP2: 47 (0x2f) for GCN 1.0/1.1<br />
    670 Opcode VOP3a: 303 (0x12f) for GCN 1.0/1.1<br />
     670Opcode VOP3A: 303 (0x12f) for GCN 1.0/1.1<br />
    671671Syntax: V_CVT_PKRTZ_F16_F32 VDST, SRC0, SRC1<br />
    672672Description: Convert normalized FP value from SRC0 and SRC1 to half floating points with
     
    679679<h4>V_CVT_PK_U16_U32</h4>
    680680<p>Opcode VOP2: 48 (0x30) for GCN 1.0/1.1<br />
    681 Opcode VOP3a: 304 (0x130) for GCN 1.0/1.1<br />
     681Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1<br />
    682682Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1<br />
    683683Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
     
    689689<h4>V_CVT_PK_I16_I32</h4>
    690690<p>Opcode VOP2: 49 (0x31) for GCN 1.0/1.1<br />
    691 Opcode VOP3a: 305 (0x131) for GCN 1.0/1.1<br />
     691Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1<br />
    692692Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1<br />
    693693Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
     
    699699<h4>V_LDEXP_F32</h4>
    700700<p>Opcode VOP2: 43 (0x2b) for GCN 1.0/1.1<br />
    701 Opcode VOP3a: 299 (0x12b) for GCN 1.0/1.1<br />
     701Opcode VOP3A: 299 (0x12b) for GCN 1.0/1.1<br />
    702702Syntax: V_LDEXP_F32 VDST, SRC0, SRC1<br />
    703703Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)).
     
    707707<h4>V_LSHL_B32</h4>
    708708<p>Opcode VOP2: 25 (0x19) for GCN 1.0/1.1<br />
    709 Opcode VOP3a: 281 (0x119) for GCN 1.0/1.1<br />
     709Opcode VOP3A: 281 (0x119) for GCN 1.0/1.1<br />
    710710Syntax: V_LSHL_B32 VDST, SRC0, SRC1<br />
    711711Description: Shift left SRC0 by (SRC1&amp;31) bits and store result into VDST.<br />
     
    714714<h4>V_LSHLREV_B32</h4>
    715715<p>Opcode VOP2: 26 (0x1a) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2<br />
    716 Opcode VOP3a: 282 (0x11a) for GCN 1.0/1.1; 274 (0x112) for GCN 1.2<br />
     716Opcode VOP3A: 282 (0x11a) for GCN 1.0/1.1; 274 (0x112) for GCN 1.2<br />
    717717Syntax: V_LSHLREV_B32 VDST, SRC0, SRC1<br />
    718718Description: Shift left SRC1 by (SRC0&amp;31) bits and store result into VDST.<br />
     
    721721<h4>V_LSHR_B32</h4>
    722722<p>Opcode VOP2: 21 (0x15) for GCN 1.0/1.1<br />
    723 Opcode VOP3a: 277 (0x115) for GCN 1.0/1.1<br />
     723Opcode VOP3A: 277 (0x115) for GCN 1.0/1.1<br />
    724724Syntax: V_LSHR_B32 VDST, SRC0, SRC1<br />
    725725Description: Shift right SRC0 by (SRC1&amp;31) bits and store result into VDST.<br />
     
    728728<h4>V_LSHRREV_B32</h4>
    729729<p>Opcode VOP2: 22 (0x16) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
    730 Opcode VOP3a: 278 (0x116) for GCN 1.0/1.1; 272 (0x110) for GCN 1.2<br />
     730Opcode VOP3A: 278 (0x116) for GCN 1.0/1.1; 272 (0x110) for GCN 1.2<br />
    731731Syntax: V_LSHRREV_B32 VDST, SRC0, SRC1<br />
    732732Description: Shift right SRC1 by (SRC0&amp;31) bits and store result into VDST.<br />
     
    735735<h4>V_MAC_F32</h4>
    736736<p>Opcode VOP2: 31 (0x1f) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2<br />
    737 Opcode VOP3a: 287 (0x11f) for GCN 1.0/1.1; 278 (0x116) for GCN 1.2<br />
     737Opcode VOP3A: 287 (0x11f) for GCN 1.0/1.1; 278 (0x116) for GCN 1.2<br />
    738738Syntax: V_MAC_F32 VDST, SRC0, SRC1<br />
    739739Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST.<br />
     
    742742<h4>V_MAC_LEGACY_F32</h4>
    743743<p>Opcode VOP2: 6 (0x6) for GCN 1.0/1.1<br />
    744 Opcode VOP3a: 262 (0x106) for GCN 1.0/1.1<br />
     744Opcode VOP3A: 262 (0x106) for GCN 1.0/1.1<br />
    745745Syntax: V_MAC_LEGACY_F32 VDST, SRC0, SRC1<br />
    746746Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST.
     
    751751<h4>V_MADMK_F32</h4>
    752752<p>Opcode: VOP2: 32 (0x20) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2<br />
    753 Opcode: VOP3a: 288 (0x120) for GCN 1.0/1.1; 279 (0x117) for GCN 1.2<br />
     753Opcode: VOP3A: 288 (0x120) for GCN 1.0/1.1; 279 (0x117) for GCN 1.2<br />
    754754Syntax: V_MADMK_F32 VDST, SRC0, FLOATLIT, SRC1<br />
    755755Description: Multiply FP value from SRC0 with the constant literal FLOATLIT and add
     
    760760<h4>V_MADAK_F32</h4>
    761761<p>Opcode: VOP2: 33 (0x21) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2<br />
    762 Opcode: VOP3a: 289 (0x121) for GCN 1.0/1.1; 280 (0x118) for GCN 1.2<br />
     762Opcode: VOP3A: 289 (0x121) for GCN 1.0/1.1; 280 (0x118) for GCN 1.2<br />
    763763Syntax: V_MADAK_F32 VDST, SRC0, SRC1, FLOATLIT<br />
    764764Description: Multiply FP value from SRC0 with FP value from SRC1 and add
     
    769769<h4>V_MAX_F32</h4>
    770770<p>Opcode VOP2: 16 (0x10) for GCN 1.0/1.1; 11 (0xb) for GCN 1.2<br />
    771 Opcode VOP3a: 272 (0x110) for GCN 1.0/1.1; 267 (0x10b) for GCN 1.2<br />
     771Opcode VOP3A: 272 (0x110) for GCN 1.0/1.1; 267 (0x10b) for GCN 1.2<br />
    772772Syntax: V_MAX_F32 VDST, SRC0, SRC1<br />
    773773Description: Choose largest floating point value from SRC0 and SRC1,
     
    777777<h4>V_MAX_I32</h4>
    778778<p>Opcode VOP2: 18 (0x12) for GCN 1.0/1.1; 13 (0xd) for GCN 1.2<br />
    779 Opcode VOP3a: 274 (0x112) for GCN 1.0/1.1; 269 (0x10d) for GCN 1.2<br />
     779Opcode VOP3A: 274 (0x112) for GCN 1.0/1.1; 269 (0x10d) for GCN 1.2<br />
    780780Syntax: V_MAX_I32 VDST, SRC0, SRC1<br />
    781781Description: Choose largest signed value from SRC0 and SRC1, and store result to VDST.<br />
     
    784784<h4>V_MAX_LEGACY_F32</h4>
    785785<p>Opcode VOP2: 14 (0xe) for GCN 1.0/1.1<br />
    786 Opcode VOP3a: 270 (0x10e) for GCN 1.0/1.1<br />
     786Opcode VOP3A: 270 (0x10e) for GCN 1.0/1.1<br />
    787787Syntax: V_MAX_LEGACY_F32 VDST, SRC0, SRC1<br />
    788788Description: Choose largest floating point value from SRC0 and SRC1,
     
    796796<h4>V_MAX_U32</h4>
    797797<p>Opcode VOP2: 20 (0x14) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
    798 Opcode VOP3a: 276 (0x114) for GCN 1.0/1.1; 271 (0x10f) for GCN 1.2<br />
     798Opcode VOP3A: 276 (0x114) for GCN 1.0/1.1; 271 (0x10f) for GCN 1.2<br />
    799799Syntax: V_MAX_U32 VDST, SRC0, SRC1<br />
    800800Description: Choose largest unsigned value from SRC0 and SRC1, and store result to VDST.<br />
     
    803803<h4>V_MBCNT_HI_U32_B32</h4>
    804804<p>Opcode VOP2: 36 (0x24) for GCN 1.0/1.1<br />
    805 Opcode VOP3a: 292 (0x124) for GCN 1.0/1.1<br />
     805Opcode VOP3A: 292 (0x124) for GCN 1.0/1.1<br />
    806806Syntax: V_MBCNT_HI_U32_B32 VDST, SRC0, SRC1<br />
    807807Description: Make mask for all lanes ending at current lane,
     
    813813<h4>V_MBCNT_LO_U32_B32</h4>
    814814<p>Opcode VOP2: 35 (0x23) for GCN 1.0/1.1<br />
    815 Opcode VOP3a: 291 (0x123) for GCN 1.0/1.1<br />
     815Opcode VOP3A: 291 (0x123) for GCN 1.0/1.1<br />
    816816Syntax: V_MBCNT_LO_U32_B32 VDST, SRC0, SRC1<br />
    817817Description: Make mask for all lanes ending at current lane,
     
    823823<h4>V_MIN_F32</h4>
    824824<p>Opcode VOP2: 15 (0xf) for GCN 1.0/1.1; 10 (0xa) for GCN 1.2<br />
    825 Opcode VOP3a: 271 (0x10f) for GCN 1.0/1.1; 266 (0x10a) for GCN 1.2<br />
     825Opcode VOP3A: 271 (0x10f) for GCN 1.0/1.1; 266 (0x10a) for GCN 1.2<br />
    826826Syntax: V_MIN_F32 VDST, SRC0, SRC1<br />
    827827Description: Choose smallest floating point value from SRC0 and SRC1,
     
    831831<h4>V_MIN_I32</h4>
    832832<p>Opcode VOP2: 17 (0x11) for GCN 1.0/1.1; 12 (0xc) for GCN 1.2<br />
    833 Opcode VOP3a: 273 (0x111) for GCN 1.0/1.1; 268 (0x10c) for GCN 1.2<br />
     833Opcode VOP3A: 273 (0x111) for GCN 1.0/1.1; 268 (0x10c) for GCN 1.2<br />
    834834Syntax: V_MIN_I32 VDST, SRC0, SRC1<br />
    835835Description: Choose smallest signed value from SRC0 and SRC1, and store result to VDST.<br />
     
    838838<h4>V_MIN_LEGACY_F32</h4>
    839839<p>Opcode VOP2: 13 (0xd) for GCN 1.0/1.1<br />
    840 Opcode VOP3a: 269 (0x10d) for GCN 1.0/1.1<br />
     840Opcode VOP3A: 269 (0x10d) for GCN 1.0/1.1<br />
    841841Syntax: V_MIN_LEGACY_F32 VDST, SRC0, SRC1<br />
    842842Description: Choose smallest floating point value from SRC0 and SRC1,
     
    850850<h4>V_MIN_U32</h4>
    851851<p>Opcode VOP2: 19 (0x13) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
    852 Opcode VOP3a: 275 (0x113) for GCN 1.0/1.1; 270 (0x10e) for GCN 1.2<br />
     852Opcode VOP3A: 275 (0x113) for GCN 1.0/1.1; 270 (0x10e) for GCN 1.2<br />
    853853Syntax: V_MIN_U32 VDST, SRC0, SRC1<br />
    854854Description: Choose smallest unsigned value from SRC0 and SRC1, and store result to VDST.<br />
     
    857857<h4>V_MUL_LEGACY_F32</h4>
    858858<p>Opcode VOP2: 7 (0x7) for GCN 1.0/1.1; 5 (0x4) for GCN 1.2<br />
    859 Opcode VOP3a: 263 (0x107) for GCN 1.0/1.1; 260 (0x104) for GCN 1.2<br />
     859Opcode VOP3A: 263 (0x107) for GCN 1.0/1.1; 260 (0x104) for GCN 1.2<br />
    860860Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1<br />
    861861Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST.
     
    868868<h4>V_MUL_F32</h4>
    869869<p>Opcode VOP2: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2<br />
    870 Opcode VOP3a: 264 (0x108) for GCN 1.0/1.1; 261 (0x105) for GCN 1.2<br />
     870Opcode VOP3A: 264 (0x108) for GCN 1.0/1.1; 261 (0x105) for GCN 1.2<br />
    871871Syntax: V_MUL_F32 VDST, SRC0, SRC1<br />
    872872Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST.<br />
     
    875875<h4>V_MUL_HI_I32_I24</h4>
    876876<p>Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2<br />
    877 Opcode VOP3a: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2<br />
     877Opcode VOP3A: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2<br />
    878878Syntax: V_MUL_HI_I32_I24 VDST, SRC0, SRC1<br />
    879879Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
     
    886886<h4>V_MUL_HI_U32_U24</h4>
    887887<p>Opcode VOP2: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2<br />
    888 Opcode VOP3a: 268 (0x10c) for GCN 1.0/1.1; 265 (0x109) for GCN 1.2<br />
     888Opcode VOP3A: 268 (0x10c) for GCN 1.0/1.1; 265 (0x109) for GCN 1.2<br />
    889889Syntax: V_MUL_HI_U32_U24 VDST, SRC0, SRC1<br />
    890890Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
     
    895895<h4>V_MUL_I32_I24</h4>
    896896<p>Opcode VOP2: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2<br />
    897 Opcode VOP3a: 265 (0x109) for GCN 1.0/1.1; 262 (0x106) for GCN 1.2<br />
     897Opcode VOP3A: 265 (0x109) for GCN 1.0/1.1; 262 (0x106) for GCN 1.2<br />
    898898Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1<br />
    899899Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
     
    905905<h4>V_MUL_U32_U24</h4>
    906906<p>Opcode VOP2: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2<br />
    907 Opcode VOP3a: 267 (0x10b) for GCN 1.0/1.1; 264 (0x108) for GCN 1.2<br />
     907Opcode VOP3A: 267 (0x10b) for GCN 1.0/1.1; 264 (0x108) for GCN 1.2<br />
    908908Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1<br />
    909909Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
     
    913913<h4>V_OR_B32</h4>
    914914<p>Opcode: VOP2: 28 (0x1c) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2<br />
    915 Opcode: VOP3a: 284 (0x11c) for GCN 1.0/1.1; 276 (0x114) for GCN 1.2<br />
     915Opcode: VOP3A: 284 (0x11c) for GCN 1.0/1.1; 276 (0x114) for GCN 1.2<br />
    916916Syntax: V_OR_B32 VDST, SRC0, SRC1<br />
    917917Description: Do bitwise OR operation on SRC0 and SRC1, store result to VDST.
     
    921921<h4>V_READLANE_B32</h4>
    922922<p>Opcode VOP2: 1 (0x1) for GCN 1.0/1.1<br />
    923 Opcode VOP3a: 257 (0x101) for GCN 1.0/1.1<br />
     923Opcode VOP3A: 257 (0x101) for GCN 1.0/1.1<br />
    924924Syntax: V_READLANE_B32 SDST, VSRC0, SSRC1<br />
    925925Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) choosen from SSRC1&amp;63.
     
    929929<h4>V_SUB_F32</h4>
    930930<p>Opcode VOP2: 4 (0x4) for GCN 1.0/1.1; 2 (0x2) for GCN 1.2<br />
    931 Opcode VOP3a: 260 (0x104) for GCN 1.0/1.1; 258 (0x102) for GCN 1.2<br />
     931Opcode VOP3A: 260 (0x104) for GCN 1.0/1.1; 258 (0x102) for GCN 1.2<br />
    932932Syntax: V_SUB_F32 VDST, SRC0, SRC1<br />
    933933Description: Subtract FP value of SRC1 from FP value of SRC0 and store result to VDST.<br />
     
    936936<h4>V_SUB_I32, V_SUB_U32</h4>
    937937<p>Opcode VOP2: 38 (0x26) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2<br />
    938 Opcode VOP3b: 294 (0x126) for GCN 1.0/1.1; 282 (0x11a) for GCN 1.2<br />
     938Opcode VOP3B: 294 (0x126) for GCN 1.0/1.1; 282 (0x11a) for GCN 1.2<br />
    939939Syntax VOP2 GCN 1.0/1.1: V_SUB_I32 VDST, VCC, SRC0, SRC1<br />
    940 Syntax VOP3b GCN 1.0/1.1: V_SUB_I32 VDST, SDST(2), SRC0, SRC1<br />
     940Syntax VOP3B GCN 1.0/1.1: V_SUB_I32 VDST, SDST(2), SRC0, SRC1<br />
    941941Syntax VOP2 GCN 1.2: V_SUB_U32 VDST, VCC, SRC0, SRC1<br />
    942 Syntax VOP3b GCN 1.2: V_SUB_U32 VDST, SDST(2), SRC0, SRC1<br />
     942Syntax VOP3B GCN 1.2: V_SUB_U32 VDST, SDST(2), SRC0, SRC1<br />
    943943Description: Subtract SRC1 from SRC0 and store result to VDST and store borrow flag to
    944944SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit.<br />
     
    950950<h4>V_SUBB_U32</h4>
    951951<p>Opcode VOP2: 41 (0x29) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
    952 Opcode VOP3b: 297 (0x129) for GCN 1.0/1.1; 285 (0x11d) for GCN 1.2<br />
     952Opcode VOP3B: 297 (0x129) for GCN 1.0/1.1; 285 (0x11d) for GCN 1.2<br />
    953953Syntax VOP2 GCN 1.0/1.1: V_SUBB_U32 VDST, VCC, SRC0, SRC1, VCC<br />
    954 Syntax VOP3b GCN 1.2: V_SUBB_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
     954Syntax VOP3B GCN 1.2: V_SUBB_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
    955955Description: Subtract SRC1 with borrow from SRC0,
    956956and store result to VDST and store carry flag to SDST (or VCC) bit with number
     
    965965<h4>V_SUBBREV_U32</h4>
    966966<p>Opcode VOP2: 42 (0x2a) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br />
    967 Opcode VOP3b: 298 (0x12a) for GCN 1.0/1.1; 286 (0x11e) for GCN 1.2<br />
     967Opcode VOP3B: 298 (0x12a) for GCN 1.0/1.1; 286 (0x11e) for GCN 1.2<br />
    968968Syntax VOP2 GCN 1.0/1.1: V_SUBBREV_U32 VDST, VCC, SRC0, SRC1, VCC<br />
    969 Syntax VOP3b GCN 1.2: V_SUBBREV_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
     969Syntax VOP3B GCN 1.2: V_SUBBREV_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2)<br />
    970970Description: Subtract SRC0 with borrow from SRC1,
    971971and store result to VDST and store carry flag to SDST (or VCC) bit with number
     
    980980<h4>V_SUBREV_F32</h4>
    981981<p>Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2<br />
    982 Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2<br />
     982Opcode VOP3A: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2<br />
    983983Syntax: V_SUBREV_F32 VDST, SRC0, SRC1<br />
    984984Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST.<br />
     
    987987<h4>V_SUBREV_I32, V_SUBREV_U32</h4>
    988988<p>Opcode VOP2: 39 (0x27) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2<br />
    989 Opcode VOP3b: 295 (0x127) for GCN 1.0/1.1; 283 (0x11b) for GCN 1.2<br />
     989Opcode VOP3B: 295 (0x127) for GCN 1.0/1.1; 283 (0x11b) for GCN 1.2<br />
    990990Syntax VOP2 GCN 1.0/1.1: V_SUBREV_I32 VDST, VCC, SRC0, SRC1<br />
    991 Syntax VOP3b GCN 1.0/1.1: V_SUBREV_I32 VDST, SDST(2), SRC0, SRC1<br />
     991Syntax VOP3B GCN 1.0/1.1: V_SUBREV_I32 VDST, SDST(2), SRC0, SRC1<br />
    992992Syntax VOP2 GCN 1.2: V_SUBREV_U32 VDST, VCC, SRC0, SRC1<br />
    993 Syntax VOP3b GCN 1.2: V_SUBREV_U32 VDST, SDST(2), SRC0, SRC1<br />
     993Syntax VOP3B GCN 1.2: V_SUBREV_U32 VDST, SDST(2), SRC0, SRC1<br />
    994994Description: Subtract SRC0 from SRC1 and store result to VDST and store borrow flag to
    995995SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit.<br />
     
    10011001<h4>V_XOR_B32</h4>
    10021002<p>Opcode: VOP2: 29 (0x1d) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br />
    1003 Opcode: VOP3a: 285 (0x11d) for GCN 1.0/1.1; 277 (0x115) for GCN 1.2<br />
     1003Opcode: VOP3A: 285 (0x11d) for GCN 1.0/1.1; 277 (0x115) for GCN 1.2<br />
    10041004Syntax: V_XOR_B32 VDST, SRC0, SRC1<br />
    10051005Description: Do bitwise XOR operation on SRC0 and SRC1, store result to VDST.
     
    10091009<h4>V_WRITELANE_B32</h4>
    10101010<p>Opcode VOP2: 2 (0x2) for GCN 1.0/1.1<br />
    1011 Opcode VOP3a: 258 (0x102) for GCN 1.0/1.1<br />
     1011Opcode VOP3A: 258 (0x102) for GCN 1.0/1.1<br />
    10121012Syntax: V_WRITELANE_B32 VDST, VSRC0, SSRC1<br />
    10131013Description: Copy SGPR to one lane of VDST. Lane choosen (thread id) from SSRC1&amp;63.