Changes between Version 14 and Version 15 of GcnInstrsVop2

Timestamp:

12/03/15 00:00:16 (8 years ago)

Author:

trac

Comment:

--

GcnInstrsVop2

@@ -191 +191 @@
 </ul>
 <p>NOTE: OMOD modifier doesn't work if output denormals are allowed
-(5 bit of MODE register for single precision or 7 bit for double precision).</p>
+(5 bit of MODE register for single precision or 7 bit for double precision).<br />
+NOTE: OMOD and CLAMP modifier affects only for instruction that output is
+floating point value.</p>
 <p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and
 OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p>
@@ -569 +571 @@
 Opcode: VOP3A: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2<br />
 Syntax: V_AND_B32 VDST, SRC0, SRC1<br />
-Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.
-CLAMP and OMOD modifier doesn't affect on result.<br />
+Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.<br />
 Operation:<br />
 <code>VDST = SRC0 &amp; SRC1</code></p>
@@ -608 +609 @@
 Syntax VOP3A: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2)<br />
 Description: If bit for current lane of VCC or SDST is set then store SRC1 to VDST,
-otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.<br />
+otherwise store SRC0 to VDST.<br />
 Operation:<br />
 <code>VDST = SSRC2&amp;(1ULL&lt;&lt;LANEID) ? SRC1 : SRC0</code></p>
@@ -881 +882 @@
 Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
 from SRC1 and store higher 16-bit of the result to VDST.
-Any modifier doesn't affect to result.<br />
+Any modifier doesn't affect on result.<br />
 Operation:<br />
 <code>VDST = ((UINT64)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff)) &gt;&gt; 32</code></p>
@@ -889 +890 @@
 Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1<br />
 Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
-and store result to VDST. Any modifier doesn't affect to result.<br />
+and store result to VDST. Any modifier doesn't affect on result.<br />
 Operation:<br />
 <code>INT32 V0 = (INT32)((SRC0&amp;0x7fffff) | (SSRC0&amp;0x800000 ? 0xff800000 : 0))
@@ -899 +900 @@
 Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1<br />
 Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
-from SRC1 and store result to VDST. Any modifier doesn't affect to result.<br />
+from SRC1 and store result to VDST. Any modifier doesn't affect on result.<br />
 Operation:<br />
 <code>VDST = (UINT32)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff)</code></p>