Changes between Version 14 and Version 15 of GcnInstrsVop2


Ignore:
Timestamp:
Dec 3, 2015, 12:00:16 AM (4 years ago)
Author:
trac
Comment:

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  • GcnInstrsVop2

    v14 v15  
    191191</ul>
    192192<p>NOTE: OMOD modifier doesn't work if output denormals are allowed
    193 (5 bit of MODE register for single precision or 7 bit for double precision).</p>
     193(5 bit of MODE register for single precision or 7 bit for double precision).<br />
     194NOTE: OMOD and CLAMP modifier affects only for instruction that output is
     195floating point value.</p>
    194196<p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and
    195197OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p>
     
    569571Opcode: VOP3A: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2<br />
    570572Syntax: V_AND_B32 VDST, SRC0, SRC1<br />
    571 Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.
    572 CLAMP and OMOD modifier doesn't affect on result.<br />
     573Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.<br />
    573574Operation:<br />
    574575<code>VDST = SRC0 &amp; SRC1</code></p>
     
    608609Syntax VOP3A: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2)<br />
    609610Description: If bit for current lane of VCC or SDST is set then store SRC1 to VDST,
    610 otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.<br />
     611otherwise store SRC0 to VDST.<br />
    611612Operation:<br />
    612613<code>VDST = SSRC2&amp;(1ULL&lt;&lt;LANEID) ? SRC1 : SRC0</code></p>
     
    881882Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
    882883from SRC1 and store higher 16-bit of the result to VDST.
    883 Any modifier doesn't affect to result.<br />
     884Any modifier doesn't affect on result.<br />
    884885Operation:<br />
    885886<code>VDST = ((UINT64)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff)) &gt;&gt; 32</code></p>
     
    889890Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1<br />
    890891Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
    891 and store result to VDST. Any modifier doesn't affect to result.<br />
     892and store result to VDST. Any modifier doesn't affect on result.<br />
    892893Operation:<br />
    893894<code>INT32 V0 = (INT32)((SRC0&amp;0x7fffff) | (SSRC0&amp;0x800000 ? 0xff800000 : 0))
     
    899900Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1<br />
    900901Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
    901 from SRC1 and store result to VDST. Any modifier doesn't affect to result.<br />
     902from SRC1 and store result to VDST. Any modifier doesn't affect on result.<br />
    902903Operation:<br />
    903904<code>VDST = (UINT32)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff)</code></p>