Changes between Version 15 and Version 16 of GcnInstrsVop2


Ignore:
Timestamp:
12/03/15 20:00:23 (8 years ago)
Author:
trac
Comment:

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  • GcnInstrsVop2

    v15 v16  
    193193(5 bit of MODE register for single precision or 7 bit for double precision).<br />
    194194NOTE: OMOD and CLAMP modifier affects only for instruction that output is
    195 floating point value.</p>
     195floating point value.<br />
     196NOTE: ABS and negation is applied to source operand for any instruction.</p>
    196197<p>Negation and absolute value can be combined: <code>-ABS(V0)</code>. Modifiers CLAMP and
    197198OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.</p>
    … …  
    612613Operation:<br />
    613614<code>VDST = SSRC2&amp;(1ULL&lt;&lt;LANEID) ? SRC1 : SRC0</code></p>
     615<h4>V_CVT_PK_I16_I32</h4>
     616<p>Opcode VOP2: 49 (0x31) for GCN 1.0/1.1<br />
     617Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1<br />
     618Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1<br />
     619Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
     620clamping, and store first value to low 16-bit and second to high 16-bit of the VDST.<br />
     621Operation:<br />
     622<code>INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000)
     623INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000)
     624VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
     625<h4>V_CVT_PK_U16_U32</h4>
     626<p>Opcode VOP2: 48 (0x30) for GCN 1.0/1.1<br />
     627Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1<br />
     628Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1<br />
     629Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
     630clamping, and store first value to low 16-bit and second to high 16-bit of the VDST.<br />
     631Operation:<br />
     632<code>UINT16 D0 = MIN(SRC0, 0xffff)
     633UINT16 D1 = MIN(SRC1, 0xffff)
     634VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
    614635<h4>V_CVT_PKACCUM_U8_F32</h4>
    615636<p>Opcode VOP2: 44 (0x2c) for GCN 1.0/1.1<br />
    … …  
    668689<code>UINT16 D0 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC0)))
    669690UINT16 D1 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC1)))
    670 VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
    671 <h4>V_CVT_PK_U16_U32</h4>
    672 <p>Opcode VOP2: 48 (0x30) for GCN 1.0/1.1<br />
    673 Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1<br />
    674 Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1<br />
    675 Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
    676 clamping, and store first value to low 16-bit and second to high 16-bit of the VDST.<br />
    677 Operation:<br />
    678 <code>UINT16 D0 = MIN(SRC0, 0xffff)
    679 UINT16 D1 = MIN(SRC1, 0xffff)
    680 VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
    681 <h4>V_CVT_PK_I16_I32</h4>
    682 <p>Opcode VOP2: 49 (0x31) for GCN 1.0/1.1<br />
    683 Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1<br />
    684 Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1<br />
    685 Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
    686 clamping, and store first value to low 16-bit and second to high 16-bit of the VDST.<br />
    687 Operation:<br />
    688 <code>INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000)
    689 INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000)
    690691VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
    691692<h4>V_LDEXP_F32</h4>