Changes between Version 2 and Version 3 of GcnInstrsVop2


Ignore:
Timestamp:
Nov 20, 2015, 9:00:19 PM (5 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GcnInstrsVop2

    v2 v3  
    300300Syntax VOP3a: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2)<br />
    301301Description: If bit for current thread of VCC or SDST is set then store SRC1 to VDST,
    302 otherwise store SRC0 to VDST.<br />
     302otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.<br />
    303303Operation:
    304304<code>VDST = SSRC2&amp;(1ULL&lt;&lt;THREADID) ? SRC1 : SRC0</code></p>
     305<h4>V_READLANE_B32</h4>
     306<p>Opcode VOP2: 1 (0x1) for GCN 1.0/1.1<br />
     307Opcode VOP3a: 257 (0x101) for GCN 1.0/1.1<br />
     308Syntax: V_READLANE_B32 SDST, VSRC0, SSRC1<br />
     309Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) choosen from SSRC1&amp;63.
     310SSRC1 can be SGPR or M0.<br />
     311Operation:<br />
     312<code>SDST = VSRC0[SSRC1 &amp; 63]</code></p>
     313<h4>V_WRITELANE_B32</h4>
     314<p>Opcode VOP2: 2 (0x2) for GCN 1.0/1.1<br />
     315Opcode VOP3a: 258 (0x102) for GCN 1.0/1.1<br />
     316Syntax: V_WRITELANE_B32 VDST, VSRC0, SSRC1<br />
     317Description: Copy SGPR to one lane of VDST. Lane choosen (thread id) from SSRC1&amp;63.
     318SSRC1 can be SGPR or M0.<br />
     319Operation:<br />
     320<code>VDST[SSRC1 &amp; 63] = SSRC0</code></p>
    305321<h4>V_SUB_F32</h4>
    306322<p>Opcode VOP2: 4 (0x4) for GCN 1.0/1.1; 2 (0x2) for GCN 1.2<br />
    307323Opcode VOP3a: 260 (0x104) for GCN 1.0/1.1; 258 (0x102) for GCN 1.2<br />
    308324Syntax: V_SUB_F32 VDST, SRC0, SRC1<br />
    309 Description: Subtract two FP value from SRC0 and SRC1 and store result to VDST.<br />
     325Description: Subtract FP value from SRC0 and FP value from SRC1 and store result to VDST.<br />
    310326Operation:<br />
    311327<code>VDST = (FLOAT)SRC0 - (FLOAT)SRC1</code></p>