| 313 | <h4>V_MAC_LEGACY_F32</h4> |
| 314 | <p>Opcode VOP2: 6 (0x6) for GCN 1.0/1.1 |
| 315 | Opcode VOP3a: 262 (0x106) for GCN 1.0/1.1 |
| 316 | Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1<br /> |
| 317 | Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST. |
| 318 | If one of value is 0.0 then always do not change VDST (do not apply IEEE rules for 0.0*x).<br /> |
| 319 | Operation:<br /> |
| 320 | <code>if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0) |
| 321 | VDST = (FLOAT)SRC0 * (FLOAT)SRC1 + (FLOAT)VDST</code></p> |
| 322 | <h4>V_MUL_LEGACY_F32</h4> |
| 323 | <p>Opcode VOP2: 7 (0x7) for GCN 1.0/1.1; 5 (0x4) for GCN 1.2<br /> |
| 324 | Opcode VOP3a: 263 (0x107) for GCN 1.0/1.1; 260 (0x104) for GCN 1.2<br /> |
| 325 | Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1<br /> |
| 326 | Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST. |
| 327 | If one of value is 0.0 then always store 0.0 to VDST (do not apply IEEE rules for 0.0*x).<br /> |
| 328 | Operation:<br /> |
| 329 | <code>if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0) |
| 330 | VDST = (FLOAT)SRC0 * (FLOAT)SRC1 |
| 331 | else |
| 332 | VDST = 0.0</code></p> |
| 333 | <h4>V_MUL_F32</h4> |
| 334 | <p>Opcode VOP2: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2<br /> |
| 335 | Opcode VOP3a: 264 (0x108) for GCN 1.0/1.1; 261 (0x105) for GCN 1.2<br /> |
| 336 | Syntax: V_MUL_F32 VDST, SRC0, SRC1<br /> |
| 337 | Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST.<br /> |
| 338 | Operation:<br /> |
| 339 | <code>VDST = (FLOAT)SRC0 * (FLOAT)SRC1</code></p> |
| 340 | <h4>V_MUL_HI_I32_24</h4> |
| 341 | <p>Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2<br /> |
| 342 | Opcode VOP3a: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2<br /> |
| 343 | Syntax: V_MUL_HI_I32_24 VDST, SRC0, SRC1<br /> |
| 344 | Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1 |
| 345 | and store higher 16-bit of the result to VDST with sign extension. |
| 346 | Any modifier doesn't affect on result.<br /> |
| 347 | Operation:<br /> |
| 348 | <code>INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0)) |
| 349 | INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0)) |
| 350 | VDST = ((INT64)V0 * V1)>>32</code></p> |
| 351 | <h4>V_MUL_HI_U32_U24</h4> |
| 352 | <p>Opcode VOP2: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2<br /> |
| 353 | Opcode VOP3a: 268 (0x10c) for GCN 1.0/1.1; 265 (0x109) for GCN 1.2<br /> |
| 354 | Syntax: V_MUL_HI_U32_U24 VDST, SRC0, SRC1<br /> |
| 355 | Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value |
| 356 | from SRC1 and store higher 16-bit of the result to VDST. |
| 357 | Any modifier doesn't affect to result.<br /> |
| 358 | Operation:<br /> |
| 359 | <code>VDST = ((UINT64)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff)) >> 32</code></p> |
| 360 | <h4>V_MUL_I32_I24</h4> |
| 361 | <p>Opcode VOP2: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2<br /> |
| 362 | Opcode VOP3a: 265 (0x109) for GCN 1.0/1.1; 262 (0x106) for GCN 1.2<br /> |
| 363 | Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1<br /> |
| 364 | Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1 |
| 365 | and store result to VDST. Any modifier doesn't affect to result.<br /> |
| 366 | Operation:<br /> |
| 367 | <code>INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0)) |
| 368 | INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0)) |
| 369 | VDST = V0 * V1</code></p> |
| 370 | <h4>V_MUL_U32_U24</h4> |
| 371 | <p>Opcode VOP2: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2<br /> |
| 372 | Opcode VOP3a: 267 (0x10b) for GCN 1.0/1.1; 264 (0x108) for GCN 1.2<br /> |
| 373 | Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1<br /> |
| 374 | Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value |
| 375 | from SRC1 and store result to VDST. Any modifier doesn't affect to result.<br /> |
| 376 | Operation:<br /> |
| 377 | <code>VDST = (UINT32)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff)</code></p> |