Changes between Version 1 and Version 2 of GcnInstrsVop3


Ignore:
Timestamp:
Dec 5, 2015, 4:00:22 PM (4 years ago)
Author:
trac
Comment:

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  • GcnInstrsVop3

    v1 v2  
    795795<h3>Instruction set</h3>
    796796<p>Alphabetically sorted instruction list:</p>
     797<h4>V_CUBEID_F32</h4>
     798<p>Opcode: 324 (0x144) for GCN 1.0/1.1; 452 (0x1c4) for GCN 1.2<br />
     799Syntax: V_CUBEID_F32 VDST, SRC0, SRC1, SRC2<br />
     800Description: Cubemap face identification. Determine face by comparing three single FP values:
     801SRC0 (X), SRC1 (Y), SRC2(Z). Choose highest absolute value and check whether is negative or
     802positive. Store floating point value of face ID: (DIM*2.0)+(V[DIM]&gt;=0?1:0),
     803where DIM is number of choosen dimension (X - 0, Y - 1, Z - 2);
     804V - vector = [SRC0, SRC1, SRC2].<br />
     805Operation:<br />
     806<code>FLOAT SF0 = ASFLOAT(SRC0)
     807FLOAT SF1 = ASFLOAT(SRC1)
     808FLOAT SF2 = ASFLOAT(SRC2)
     809FLOAT OUT
     810if (ABS(SF2) &gt;= ABS(SF1) &amp;&amp; ABS(SF2) &gt;= ABS(SF0))
     811    OUT = (SF2 &gt;= 0.0) ? 4 : 5
     812else if (ABS(SF1) &gt;= ABS(SF0)
     813    OUT = (SF1 &gt;= 0.0) ? 2 : 3
     814else
     815    OUT = (SF0 &gt;= 0.0) ? 0 : 1
     816VDST = OUT</code></p>
     817<h4>V_MAD_F32</h4>
     818<p>Opcode: 321 (0x141) for GCN 1.0/1.1; 449 (0x1c1) for GCN 1.2<br />
     819Syntax: V_MAD_F32 VDST, SRC0, SRC1, SRC2<br />
     820Description: Multiply FP value from SRC0 by FP value from SRC1 and add SRC2, and store
     821result to VDST.<br />
     822Operation:<br />
     823<code>VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(SRC2)</code></p>
     824<h4>V_MAD_I32_I24</h4>
     825<p>Opcode: 322 (0x142) for GCN 1.0/1.1; 450 (0x1c2) for GCN 1.2<br />
     826Syntax: V_MAD_I32_I24 VDST, SRC0, SRC1, SRC2<br />
     827Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1,
     828add SRC2 to this product, and and store result to VDST.<br />
     829Operation:<br />
     830<code>INT32 V0 = (INT32)((SRC0&amp;0x7fffff) | (SSRC0&amp;0x800000 ? 0xff800000 : 0))
     831INT32 V1 = (INT32)((SRC1&amp;0x7fffff) | (SSRC1&amp;0x800000 ? 0xff800000 : 0))
     832VDST = V0 * V1 + SRC2</code></p>
    797833<h4>V_MAD_LEGACY_F32</h4>
    798834<p>Opcode: 320 (0x140) for GCN 1.0/1.1; 448 (0x1c0) for GCN 1.2<br />
    799835Syntax: V_MAD_LEGACY_F32 VDST, SRC0, SRC1, SRC2<br />
    800 Description:</p>
     836Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to SRC2, and
     837store result to VDST. If one of value is 0.0 then always store SRC2 to VDST
     838(do not apply IEEE rules for 0.0*x).<br />
     839Operation:<br />
     840<code>if (ASFLOAT(SRC0)!=0.0 &amp;&amp; ASFLOAT(SRC1)!=0.0)
     841    VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(SRC2)</code></p>
     842<h4>V_MAD_U32_U24</h4>
     843<p>Opcode: 323 (0x143) for GCN 1.0/1.1; 451 (0x1c3) for GCN 1.2<br />
     844Syntax: V_MAD_U32_U24 VDST, SRC0, SRC1, SRC2<br />
     845Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
     846from SRC1, add SRC2 to this product and store result to VDST.<br />
     847Operation:<br />
     848<code>VDST = (UINT32)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff) + SRC2</code></p>
    801849}}}