Changes between Version 25 and Version 26 of GcnInstrsVop3


Ignore:
Timestamp:
Jun 17, 2017, 3:00:34 PM (2 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVop3

    v25 v26  
    10261026UINT16 D1 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC1)))
    10271027VDST = D0 | (((UINT32)D1) &lt;&lt; 16)</code></p>
     1028<h4>V_DIV_FIXUP_F16</h4>
     1029<p>Opcode: 495 (0x1ef) for GCN 1.2<br />
     1030Syntax: V_DIV_FIXUP_F16 VDST, SRC0, SRC1, SRC2<br />
     1031Description: Handle all exceptions requires for half floating point division.
     1032SRC0 is quotient, SRC1 is denominator, SRC2 is nominator. Correct result stored to VDST.<br />
     1033Operation:<br />
     1034<code>HALF SF0 = ASHALF(SRC0)
     1035HALF SF1 = ASHALF(SRC1)
     1036HALF SF2 = ASHALF(SRC2)
     1037if (ISNAN(SF1) &amp;&amp; !ISNAN(SF2))
     1038    VDST = QUIETNAN(SF1)
     1039else if (ISNAN(SF2))
     1040    VDST = QUIETNAN(SF2)
     1041else if (SF1 == 0.0 &amp;&amp; SF2 == 0.0)
     1042    VDST = NAN_H
     1043else if (ABS(SF1)==INF &amp;&amp; ABS(SF2)==INF)
     1044    VDST = -NAN_H
     1045else if (SF1 == 0.0)
     1046    VDST = INF_H*SIGN(SF1)*SIGN(SF2)
     1047else if (ABS(SF1) == INF)
     1048    VDST = SIGN(SF1)*SIGN(SF2) &gt;=0 ? 0.0 : -0.0
     1049else if (ISNAN(SF0))
     1050    VDST = SIGN(SF1)*SIGN(SF2)*INF_H
     1051else
     1052    VDST = SF0</code></p>
    10281053<h4>V_DIV_FIXUP_F32</h4>
    10291054<p>Opcode: 351 (0x15f) for GCN 1.0/1.1; 478 (0x1de) for GCN 1.2<br />
     
    11771202    SDST = (SDST &amp; ~MASK)
    11781203}</code></p>
     1204<h4>V_FMA_F16</h4>
     1205<p>Opcode: 494 (0x1ee) for GCN 1.2<br />
     1206Syntax: V_FMA_F16 VDST, SRC0, SRC1, SRC2<br />
     1207Description: Fused multiply addition on half floating point values from
     1208SRC0, SRC1 and SRC2. Result stored in VDST.<br />
     1209Operation:<br />
     1210<code>// SRC0*SRC1+SRC2
     1211VDST = FMA(ASHALF(SRC0), ASHALF(SRC1), ASHALF(SRC2))</code></p>
    11791212<h4>V_FMA_F32</h4>
    11801213<p>Opcode: 331 (0x14b) for GCN 1.0/1.1; 459 (0x1cb) for GCN 1.2<br />
     
    12531286<code>if (ASFLOAT(SRC0)!=0.0 &amp;&amp; ASFLOAT(SRC1)!=0.0)
    12541287    VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST)</code></p>
     1288<h4>V_MAD_F16</h4>
     1289<p>Opcode: 490 (0x1ea) for GCN 1.2<br />
     1290Syntax: V_MAD_F16 VDST, SRC0, SRC1, SRC2<br />
     1291Description: Multiply half FP value from SRC0 by half FP value from
     1292SRC1 and add SRC2, and store result to VDST.
     1293It applies OMOD modifier to result and it flush denormals.<br />
     1294Operation:<br />
     1295<code>VDST = ASHALF(SRC0) * ASHALF(SRC1) + ASHALF(SRC2)</code></p>
    12551296<h4>V_MAD_F32</h4>
    12561297<p>Opcode: 321 (0x141) for GCN 1.0/1.1; 449 (0x1c1) for GCN 1.2<br />