Changes between Initial Version and Version 1 of GcnInstrsVopc


Ignore:
Timestamp:
12/04/15 19:00:16 (8 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVopc

    v1 v1  
     1[wiki:ClrxToc Back to Table of content]
     2{{{
     3#!html
     4<h2>GCN ISA VOPC/VOP3 instructions</h2>
     5<p>VOPC instructions can be encoded in the VOPC encoding and the VOP3A/VOP3B encoding.
     6List of fields for VOPC encoding:</p>
     7<table>
     8<thead>
     9<tr>
     10<th>Bits</th>
     11<th>Name</th>
     12<th>Description</th>
     13</tr>
     14</thead>
     15<tbody>
     16<tr>
     17<td>0-8</td>
     18<td>SRC0</td>
     19<td>First (scalar or vector) source operand</td>
     20</tr>
     21<tr>
     22<td>9-16</td>
     23<td>VSRC1</td>
     24<td>Second (scalar or vector) source operand</td>
     25</tr>
     26<tr>
     27<td>17-24</td>
     28<td>OPCODE</td>
     29<td>Operation code</td>
     30</tr>
     31<tr>
     32<td>25-31</td>
     33<td>ENCODING</td>
     34<td>Encoding type. Must be 0b0111110</td>
     35</tr>
     36</tbody>
     37</table>
     38<p>Syntax: INSTRUCTION VCC, SRC0, VSRC1</p>
     39<p>List of fields for VOP3A/VOP3B encoding (GCN 1.0/1.1):</p>
     40<table>
     41<thead>
     42<tr>
     43<th>Bits</th>
     44<th>Name</th>
     45<th>Description</th>
     46</tr>
     47</thead>
     48<tbody>
     49<tr>
     50<td>0-7</td>
     51<td>SDST</td>
     52<td>Scalar destination operand</td>
     53</tr>
     54<tr>
     55<td>8-10</td>
     56<td>ABS</td>
     57<td>Absolute modifiers for source operands (VOP3A)</td>
     58</tr>
     59<tr>
     60<td>8-14</td>
     61<td>SDST</td>
     62<td>Scalar destination operand (VOP3B)</td>
     63</tr>
     64<tr>
     65<td>11</td>
     66<td>CLAMP</td>
     67<td>CLAMP modifier (VOP3A)</td>
     68</tr>
     69<tr>
     70<td>15</td>
     71<td>CLAMP</td>
     72<td>CLAMP modifier (VOP3B)</td>
     73</tr>
     74<tr>
     75<td>17-25</td>
     76<td>OPCODE</td>
     77<td>Operation code</td>
     78</tr>
     79<tr>
     80<td>26-31</td>
     81<td>ENCODING</td>
     82<td>Encoding type. Must be 0b110100</td>
     83</tr>
     84<tr>
     85<td>32-40</td>
     86<td>SRC0</td>
     87<td>First (scalar or vector) source operand</td>
     88</tr>
     89<tr>
     90<td>41-49</td>
     91<td>SRC1</td>
     92<td>Second (scalar or vector) source operand</td>
     93</tr>
     94<tr>
     95<td>50-58</td>
     96<td>SRC2</td>
     97<td>Third (scalar or vector) source operand</td>
     98</tr>
     99<tr>
     100<td>59-60</td>
     101<td>OMOD</td>
     102<td>OMOD modifier. Multiplication modifier</td>
     103</tr>
     104<tr>
     105<td>61-63</td>
     106<td>NEG</td>
     107<td>Negation modifier for source operands</td>
     108</tr>
     109</tbody>
     110</table>
     111<p>List of fields for VOP3A/VOP3B encoding (GCN 1.2):</p>
     112<table>
     113<thead>
     114<tr>
     115<th>Bits</th>
     116<th>Name</th>
     117<th>Description</th>
     118</tr>
     119</thead>
     120<tbody>
     121<tr>
     122<td>0-7</td>
     123<td>SDST</td>
     124<td>Scalar destination operand</td>
     125</tr>
     126<tr>
     127<td>8-10</td>
     128<td>ABS</td>
     129<td>Absolute modifiers for source operands (VOP3A)</td>
     130</tr>
     131<tr>
     132<td>8-14</td>
     133<td>SDST</td>
     134<td>Scalar destination operand (VOP3B)</td>
     135</tr>
     136<tr>
     137<td>15</td>
     138<td>CLAMP</td>
     139<td>CLAMP modifier</td>
     140</tr>
     141<tr>
     142<td>16-25</td>
     143<td>OPCODE</td>
     144<td>Operation code</td>
     145</tr>
     146<tr>
     147<td>26-31</td>
     148<td>ENCODING</td>
     149<td>Encoding type. Must be 0b110100</td>
     150</tr>
     151<tr>
     152<td>32-40</td>
     153<td>SRC0</td>
     154<td>First (scalar or vector) source operand</td>
     155</tr>
     156<tr>
     157<td>41-49</td>
     158<td>SRC1</td>
     159<td>Second (scalar or vector) source operand</td>
     160</tr>
     161<tr>
     162<td>50-58</td>
     163<td>SRC2</td>
     164<td>Third (scalar or vector) source operand</td>
     165</tr>
     166<tr>
     167<td>59-60</td>
     168<td>OMOD</td>
     169<td>OMOD modifier. Multiplication modifier</td>
     170</tr>
     171<tr>
     172<td>61-63</td>
     173<td>NEG</td>
     174<td>Negation modifier for source operands</td>
     175</tr>
     176</tbody>
     177</table>
     178<p>Syntax: INSTRUCTION SDST(2), SRC0, SRC1 [MODIFIERS]</p>
     179<p>Modifiers:</p>
     180<ul>
     181<li>-SRC - negate floating point value from source operand. Applied after ABS modifier.</li>
     182<li>ABS(SRC) - apply absolute value to source operand</li>
     183</ul>
     184<p>NOTE: ABS and negation is applied to source operand for any instruction.</p>
     185<p>Negation and absolute value can be combined: <code>-ABS(V0)</code>.</p>
     186<p>Limitations for operands:</p>
     187<ul>
     188<li>only one SGPR can be read by instruction. Multiple occurrences of this same
     189SGPR is allowed</li>
     190<li>only one literal constant can be used, and only when a SGPR or M0 is not used in
     191source operands</li>
     192<li>only SRC0 can holds LDS_DIRECT</li>
     193</ul>
     194<p>VOPC opcodes (0-255) and VOP3 opcodes are same.</p>
     195<h3>Tables of opcodes and their descriptions (GCN 1.0/1.1)</h3>
     196<p>Table of floating point comparison instructions by opcode:</p>
     197<table>
     198<thead>
     199<tr>
     200<th>Opcode range</th>
     201<th>Instruction</th>
     202<th>Description</th>
     203</tr>
     204</thead>
     205<tbody>
     206<tr>
     207<td>0-15 (0x00-0x0f)</td>
     208<td>V_CMP_{OP16}_F32</td>
     209<td>Signal on sNAN input only. Single FP values.</td>
     210</tr>
     211<tr>
     212<td>16-31 (0x10-0x1f)</td>
     213<td>V_CMPX_{OP16}_F32</td>
     214<td>Signal on sNAN input only. Write result to EXEC. Single FP values.</td>
     215</tr>
     216<tr>
     217<td>32-47 (0x20-0x2f)</td>
     218<td>V_CMP_{OP16}_F64</td>
     219<td>Signal on sNAN input only. Double FP values.</td>
     220</tr>
     221<tr>
     222<td>48-63 (0x30-0x3f)</td>
     223<td>V_CMPX_{OP16}_F64</td>
     224<td>Signal on sNAN input only. Write result to EXEC. Double FP values.</td>
     225</tr>
     226<tr>
     227<td>64-79 (0x40-0x4f)</td>
     228<td>V_CMP_{OP16}_F32</td>
     229<td>Signal on any sNAN. Single FP values.</td>
     230</tr>
     231<tr>
     232<td>80-95 (0x50-0x5f)</td>
     233<td>V_CMPX_{OP16}_F32</td>
     234<td>Signal on any sNAN. Write result to EXEC. Single FP values.</td>
     235</tr>
     236<tr>
     237<td>96-111 (0x60-0x6f)</td>
     238<td>V_CMP_{OP16}_F64</td>
     239<td>Signal on any sNAN. Double FP values.</td>
     240</tr>
     241<tr>
     242<td>112-127 (0x70-0x7f)</td>
     243<td>V_CMPX_{OP16}_F64</td>
     244<td>Signal on any sNAN. Write result to EXEC. Double FP values.</td>
     245</tr>
     246</tbody>
     247</table>
     248<p>Table of OP16 (compare operations) for floating point values comparisons:</p>
     249<table>
     250<thead>
     251<tr>
     252<th>Opcode offset</th>
     253<th>OP16 name</th>
     254<th>Description</th>
     255</tr>
     256</thead>
     257<tbody>
     258<tr>
     259<td>0 (0x0)</td>
     260<td>F</td>
     261<td>SDST(LANEID) = 0</td>
     262</tr>
     263<tr>
     264<td>1 (0x1)</td>
     265<td>LT</td>
     266<td>SDST(LANEID) = (TYPE)SRC0 &lt; (TYPE)SRC1</td>
     267</tr>
     268<tr>
     269<td>2 (0x2)</td>
     270<td>EQ</td>
     271<td>SDST(LANEID) = (TYPE)SRC0 == (TYPE)SRC1</td>
     272</tr>
     273<tr>
     274<td>3 (0x3)</td>
     275<td>LE</td>
     276<td>SDST(LANEID) = (TYPE)SRC0 &lt;= (TYPE)SRC1</td>
     277</tr>
     278<tr>
     279<td>4 (0x4)</td>
     280<td>GT</td>
     281<td>SDST(LANEID) = (TYPE)SRC0 &gt; (TYPE)SRC1</td>
     282</tr>
     283<tr>
     284<td>5 (0x5)</td>
     285<td>LG</td>
     286<td>SDST(LANEID) = (TYPE)SRC0 != (TYPE)SRC1</td>
     287</tr>
     288<tr>
     289<td>6 (0x6)</td>
     290<td>GE</td>
     291<td>SDST(LANEID) = (TYPE)SRC0 &gt;= (TYPE)SRC1</td>
     292</tr>
     293<tr>
     294<td>7 (0x7)</td>
     295<td>O</td>
     296<td>SDST(LANEID) = ((TYPE)SRC0!=NAN &amp;&amp; (TYPE)SRC1!=NAN)</td>
     297</tr>
     298<tr>
     299<td>8 (0x8)</td>
     300<td>U</td>
     301<td>SDST(LANEID) = ((TYPE)SRC0!=NAN</td>
     302</tr>
     303<tr>
     304<td>9 (0x9)</td>
     305<td>NGE</td>
     306<td>SDST(LANEID) = !((TYPE)SRC0 &gt;= (TYPE)SRC1)</td>
     307</tr>
     308<tr>
     309<td>10 (0xa)</td>
     310<td>NLG</td>
     311<td>SDST(LANEID) = !((TYPE)SRC0 != (TYPE)SRC1)</td>
     312</tr>
     313<tr>
     314<td>11 (0xb)</td>
     315<td>NGT</td>
     316<td>SDST(LANEID) = !((TYPE)SRC0 &gt; (TYPE)SRC1)</td>
     317</tr>
     318<tr>
     319<td>12 (0xc)</td>
     320<td>NLE</td>
     321<td>SDST(LANEID) = !((TYPE)SRC0 &lt;= (TYPE)SRC1)</td>
     322</tr>
     323<tr>
     324<td>13 (0xd)</td>
     325<td>NEG</td>
     326<td>SDST(LANEID) = !((TYPE)SRC0 == (TYPE)SRC1)</td>
     327</tr>
     328<tr>
     329<td>14 (0xe)</td>
     330<td>NLT</td>
     331<td>SDST(LANEID) = !((TYPE)SRC0 &lt; (TYPE)SRC1)</td>
     332</tr>
     333<tr>
     334<td>15 (0xf)</td>
     335<td>T</td>
     336<td>SDST(LANEID) = 1</td>
     337</tr>
     338</tbody>
     339</table>
     340<p>NOTE: Comparison operators (&lt;,&lt;=,!=,==) compares only non NaN values. If any operand is NaN
     341then returns false. By contrast, negations of comparisons (NLT, NGT) returns true
     342if any operand is NaN value. This feature distinguish for example NGE from LT.  </p>
     343<p>LANEID in description is lane id. TYPE is type of compared values (FLOAT for _FP32,
     344DOUBLE for _FP64).</p>
     345<p>Sample instructions:<br />
     346<code>V_CMPX_LT_F32 VCC, V0, V1  # V0&lt;V1
     347V_CMPSX_EQ_F32 VCC, V0, V1 # V0==V1, store result to EXEC, signal for any sNaN
     348V_CMPX_LT_F64 VCC, V[2:3], V[4:5]  # V[2:3]&lt;V[4:5]</code></p>
     349<p>Table of integer comparison instructions by opcode:</p>
     350<table>
     351<thead>
     352<tr>
     353<th>Opcode range</th>
     354<th>Instruction</th>
     355<th>Description</th>
     356</tr>
     357</thead>
     358<tbody>
     359<tr>
     360<td>128-135 (0x80-0x87)</td>
     361<td>V_CMP_{OP8}_I32</td>
     362<td>Signed 32-bit values.</td>
     363</tr>
     364<tr>
     365<td>144-151 (0x90-0x97)</td>
     366<td>V_CMPX_{OP8}_I32</td>
     367<td>Write result to EXEC. Signed 32-bit values.</td>
     368</tr>
     369<tr>
     370<td>160-167 (0xa0-0xa7)</td>
     371<td>V_CMP_{OP8}_I64</td>
     372<td>Signed 64-bit values.</td>
     373</tr>
     374<tr>
     375<td>176-183 (0xb0-0xb7)</td>
     376<td>V_CMPX_{OP8}_I64</td>
     377<td>Write result to EXEC. Signed 64-bit values.</td>
     378</tr>
     379<tr>
     380<td>192-199 (0xc0-0xc7)</td>
     381<td>V_CMP_{OP8}_U32</td>
     382<td>Unsigned 32-bit values.</td>
     383</tr>
     384<tr>
     385<td>208-215 (0xd0-0xd7)</td>
     386<td>V_CMPX_{OP8}_U32</td>
     387<td>Write result to EXEC. Unsigned 32-bit values.</td>
     388</tr>
     389<tr>
     390<td>224-231 (0xe0-0xe7)</td>
     391<td>V_CMP_{OP8}_U64</td>
     392<td>Unsigned 64-bit values.</td>
     393</tr>
     394<tr>
     395<td>240-247 (0xf0-0xf7)</td>
     396<td>V_CMPX_{OP8}_U64</td>
     397<td>Write result to EXEC. Unsigned 64-bit values.</td>
     398</tr>
     399</tbody>
     400</table>
     401<p>Table of OP16 (compare operations) for integer values comparisons:</p>
     402<table>
     403<thead>
     404<tr>
     405<th>Opcode offset</th>
     406<th>OP8 name</th>
     407<th>Description</th>
     408</tr>
     409</thead>
     410<tbody>
     411<tr>
     412<td>0 (0x0)</td>
     413<td>F</td>
     414<td>SDST(LANEID) = 0</td>
     415</tr>
     416<tr>
     417<td>1 (0x1)</td>
     418<td>LT</td>
     419<td>SDST(LANEID) = (TYPE)SRC0 &lt; (TYPE)SRC1</td>
     420</tr>
     421<tr>
     422<td>2 (0x2)</td>
     423<td>EQ</td>
     424<td>SDST(LANEID) = (TYPE)SRC0 == (TYPE)SRC1</td>
     425</tr>
     426<tr>
     427<td>3 (0x3)</td>
     428<td>LE</td>
     429<td>SDST(LANEID) = (TYPE)SRC0 &lt;= (TYPE)SRC1</td>
     430</tr>
     431<tr>
     432<td>4 (0x4)</td>
     433<td>GT</td>
     434<td>SDST(LANEID) = (TYPE)SRC0 &gt; (TYPE)SRC1</td>
     435</tr>
     436<tr>
     437<td>5 (0x5)</td>
     438<td>LG, NE</td>
     439<td>SDST(LANEID) = (TYPE)SRC0 != (TYPE)SRC1</td>
     440</tr>
     441<tr>
     442<td>6 (0x6)</td>
     443<td>GE</td>
     444<td>SDST(LANEID) = (TYPE)SRC0 &gt;= (TYPE)SRC1</td>
     445</tr>
     446<tr>
     447<td>7 (0x7)</td>
     448<td>T</td>
     449<td>SDST(LANEID) = 1</td>
     450</tr>
     451</tbody>
     452</table>
     453<p>LANEID in description is lane id. TYPE is type of compared values (UINT32 for _U32,
     454INT32 for _I32,...).</p>
     455<p>Sample instructions:<br />
     456<code>V_CMP_LT_U32 VCC, V0, V1  # V0&lt;V1
     457V_CMPX_EQ_U32 VCC, V0, V1 # V0==V1, store result to EXEC, signal for any sNaN</code></p>
     458<p>Table of class instructions:</p>
     459<h3>Tables of opcodes and their descriptions (GCN 1.2)</h3>
     460<h4>V_CMP_CLASS_F32</h4>
     461<p>Opcode: 0x88<br />
     462Syntax VOPC: V_CMP_CLASS_F32 VCC, SRC0, SRC1<br />
     463Syntax VOP3: V_CMP_CLASS_F32 SDST, SRC0, SRC1<br />
     464Operation: Check whether SSRC0 single floating point value belongs to one of specified class.
     465Classes are specified as set bits in SRC1. If that condition is satisfied then store
     4661 to bit of SDST with number of current lane id, otherwise clear that bit.
     467No flushing denormalized values for SRC0. List of classes:</p>
     468<table>
     469<thead>
     470<tr>
     471<th>Bit</th>
     472<th>Description</th>
     473</tr>
     474</thead>
     475<tbody>
     476<tr>
     477<td>0</td>
     478<td>Signaling NaN</td>
     479</tr>
     480<tr>
     481<td>1</td>
     482<td>quiet Nan</td>
     483</tr>
     484<tr>
     485<td>2</td>
     486<td>-INF</td>
     487</tr>
     488<tr>
     489<td>3</td>
     490<td>negative normalized value</td>
     491</tr>
     492<tr>
     493<td>4</td>
     494<td>negative dernormalized value</td>
     495</tr>
     496<tr>
     497<td>5</td>
     498<td>negative zero</td>
     499</tr>
     500<tr>
     501<td>6</td>
     502<td>positive zero</td>
     503</tr>
     504<tr>
     505<td>7</td>
     506<td>positive denormalized value</td>
     507</tr>
     508<tr>
     509<td>8</td>
     510<td>positive normalized value</td>
     511</tr>
     512<tr>
     513<td>9</td>
     514<td>+INF</td>
     515</tr>
     516</tbody>
     517</table>
     518<h4>V_CMPX_CLASS_F32</h4>
     519<p>Opcode: 0x98<br />
     520Syntax VOPC: V_CMPX_CLASS_F32 VCC, SRC0, SRC1<br />
     521Syntax VOP3: V_CMPX_CLASS_F32 SDST, SRC0, SRC1<br />
     522Operation: Check whether SSRC0 single floating point value belongs to one of specified class.
     523Classes are specified as set bits in SRC1. If that condition is satisfied then store
     5241 to bit of SDST and EXEC with number of current lane id, otherwise clear that bit.
     525No flushing denormalized values for SRC0. List of classes:</p>
     526<table>
     527<thead>
     528<tr>
     529<th>Bit</th>
     530<th>Description</th>
     531</tr>
     532</thead>
     533<tbody>
     534<tr>
     535<td>0</td>
     536<td>Signaling NaN</td>
     537</tr>
     538<tr>
     539<td>1</td>
     540<td>quiet Nan</td>
     541</tr>
     542<tr>
     543<td>2</td>
     544<td>-INF</td>
     545</tr>
     546<tr>
     547<td>3</td>
     548<td>negative normalized value</td>
     549</tr>
     550<tr>
     551<td>4</td>
     552<td>negative dernormalized value</td>
     553</tr>
     554<tr>
     555<td>5</td>
     556<td>negative zero</td>
     557</tr>
     558<tr>
     559<td>6</td>
     560<td>positive zero</td>
     561</tr>
     562<tr>
     563<td>7</td>
     564<td>positive denormalized value</td>
     565</tr>
     566<tr>
     567<td>8</td>
     568<td>positive normalized value</td>
     569</tr>
     570<tr>
     571<td>9</td>
     572<td>+INF</td>
     573</tr>
     574</tbody>
     575</table>
     576<h4>V_CMP_CLASS_F64</h4>
     577<p>Opcode: 0xa8<br />
     578Syntax VOPC: V_CMP_CLASS_F64 VCC, SRC0, SRC1(2)<br />
     579Syntax VOP3: V_CMP_CLASS_F64 SDST, SRC0(2), SRC1(2)<br />
     580Operation: Check whether SSRC0 double floating point value belongs to one of specified class.
     581Classes are specified as set bits in SRC1. If that condition is satisfied then store
     5821 to bit of SDST with number of current lane id, otherwise clear that bit.
     583No flushing denormalized values for SRC0. List of classes:</p>
     584<table>
     585<thead>
     586<tr>
     587<th>Bit</th>
     588<th>Description</th>
     589</tr>
     590</thead>
     591<tbody>
     592<tr>
     593<td>0</td>
     594<td>Signaling NaN</td>
     595</tr>
     596<tr>
     597<td>1</td>
     598<td>quiet Nan</td>
     599</tr>
     600<tr>
     601<td>2</td>
     602<td>-INF</td>
     603</tr>
     604<tr>
     605<td>3</td>
     606<td>negative normalized value</td>
     607</tr>
     608<tr>
     609<td>4</td>
     610<td>negative dernormalized value</td>
     611</tr>
     612<tr>
     613<td>5</td>
     614<td>negative zero</td>
     615</tr>
     616<tr>
     617<td>6</td>
     618<td>positive zero</td>
     619</tr>
     620<tr>
     621<td>7</td>
     622<td>positive denormalized value</td>
     623</tr>
     624<tr>
     625<td>8</td>
     626<td>positive normalized value</td>
     627</tr>
     628<tr>
     629<td>9</td>
     630<td>+INF</td>
     631</tr>
     632</tbody>
     633</table>
     634<h4>V_CMPX_CLASS_F64</h4>
     635<p>Opcode: 0xb8<br />
     636Syntax VOPC: V_CMPX_CLASS_F64 VCC, SRC0(2), SRC1(2)<br />
     637Syntax VOP3: V_CMPX_CLASS_F64 SDST, SRC0(2), SRC1(2)<br />
     638Operation: Check whether SSRC0 double floating point value belongs to one of specified class.
     639Classes are specified as set bits in SRC1. If that condition is satisfied then store
     6401 to bit of SDST and EXEC with number of current lane id, otherwise clear that bit.
     641No flushing denormalized values for SRC0. List of classes:</p>
     642<table>
     643<thead>
     644<tr>
     645<th>Bit</th>
     646<th>Description</th>
     647</tr>
     648</thead>
     649<tbody>
     650<tr>
     651<td>0</td>
     652<td>Signaling NaN</td>
     653</tr>
     654<tr>
     655<td>1</td>
     656<td>quiet Nan</td>
     657</tr>
     658<tr>
     659<td>2</td>
     660<td>-INF</td>
     661</tr>
     662<tr>
     663<td>3</td>
     664<td>negative normalized value</td>
     665</tr>
     666<tr>
     667<td>4</td>
     668<td>negative dernormalized value</td>
     669</tr>
     670<tr>
     671<td>5</td>
     672<td>negative zero</td>
     673</tr>
     674<tr>
     675<td>6</td>
     676<td>positive zero</td>
     677</tr>
     678<tr>
     679<td>7</td>
     680<td>positive denormalized value</td>
     681</tr>
     682<tr>
     683<td>8</td>
     684<td>positive normalized value</td>
     685</tr>
     686<tr>
     687<td>9</td>
     688<td>+INF</td>
     689</tr>
     690</tbody>
     691</table>
     692}}}