Changes between Version 2 and Version 3 of GcnTimings
- Timestamp:
- 01/26/16 00:00:15 (8 years ago)
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GcnTimings
v2 v3 21 21 instruction outside these first 3 dwords adds single penalty.</li> 22 22 <li>if instructions is longer (more than four cycles) then last cycles/4 dwords are free</li> 23 <li>if 16 or more cycle 2-dword instruction and 2 dword ins utrction in 4 dword, then23 <li>if 16 or more cycle 2-dword instruction and 2 dword instruction in 4 dword, then 24 24 no penalty for second 2-dword instruction.</li> 25 25 </ul> 26 <h3>Instruction scheduling</h3> 27 <p>Between any vector operation that operates on VCC and any scalar ALU instruction is 28 16-cycle delay.</p> 26 29 <h3>SOP2 Instruction timings</h3> 27 30 <table> … … 368 371 </tbody> 369 372 </table> 373 <h3>SOP1 Instruction timings</h3> 374 <p>The S_*_SAVEEXEC_B64 instructions takes 8 cycles. Other ALU instructions (expects 375 S_MOV_REGRD_B32, S_CBRANCH_JOIN, S_RFE_B64) take 4 cycles.</p> 376 <h3>SOPC Instruction timings</h3> 377 <p>All comparison and bit checking instructions take 4 cycles.</p> 370 378 }}}