Changes between Version 2 and Version 3 of GcnInstrsSmem
- Timestamp:
- 06/09/17 06:00:27 (7 years ago)
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GcnInstrsSmem
v2 v3 3 3 #!html 4 4 <h2>GCN ISA SMEM instructions (GCN 1.2)</h2> 5 <p>The basic encoding of the SMEM instructions needs 9bytes (2 dwords). List of fields:</p>5 <p>The encoding of the SMEM instructions needs 8 bytes (2 dwords). List of fields:</p> 6 6 <table> 7 7 <thead> … … 56 56 </ul> 57 57 <p>For S_LOAD_DWORD* instructions, 2 SBASE SGPRs holds an base 48-bit address and a 58 16-bit size. 59 For S_BUFFER_LOAD_DWORD* instructions, 4 SBASE SGPRs holds a buffer descriptor.60 In this case, SBASE must be a multipla of 2.</p>58 16-bit size. For S_BUFFER_LOAD_DWORD* instructions, 4 SBASE SGPRs holds a 59 buffer descriptor. In this case, SBASE must be a multipla of 2. 60 S_STORE_* and S_BUFFER_STORE_* accepts only M0 as offset register.</p> 61 61 <p>The SMEM instructions can return the result data out of the order. Any SMEM operation 62 62 (including S_MEMTIME) increments LGKM_CNT counter. The best way to wait for results