Changes between Version 11 and Version 12 of GcnInstrsSop1


Ignore:
Timestamp:
11/23/17 21:01:18 (6 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • GcnInstrsSop1

    v11 v12  
    4444<th>Mnemonic (GCN1.0/1.1)</th>
    4545<th>Mnemonic (GCN 1.2)</th>
     46<th>Mnemonic (GCN 1.4)</th>
    4647</tr>
    4748</thead>
    … …  
    5152<td>--</td>
    5253<td>S_MOV_B32</td>
     54<td>S_MOV_B32</td>
    5355</tr>
    5456<tr>
    … …  
    5658<td>--</td>
    5759<td>S_MOV_B64</td>
     60<td>S_MOV_B64</td>
    5861</tr>
    5962<tr>
    6063<td>2 (0x2)</td>
    6164<td>--</td>
     65<td>S_CMOV_B32</td>
    6266<td>S_CMOV_B32</td>
    6367</tr>
    … …  
    6670<td>S_MOV_B32</td>
    6771<td>S_CMOV_B64</td>
     72<td>S_CMOV_B64</td>
    6873</tr>
    6974<tr>
    … …  
    7176<td>S_MOV_B64</td>
    7277<td>S_NOT_B32</td>
     78<td>S_NOT_B32</td>
    7379</tr>
    7480<tr>
    … …  
    7682<td>S_CMOV_B32</td>
    7783<td>S_NOT_B64</td>
     84<td>S_NOT_B64</td>
    7885</tr>
    7986<tr>
    … …  
    8188<td>S_CMOV_B64</td>
    8289<td>S_WQM_B32</td>
     90<td>S_WQM_B32</td>
    8391</tr>
    8492<tr>
    … …  
    8694<td>S_NOT_B32</td>
    8795<td>S_WQM_B64</td>
     96<td>S_WQM_B64</td>
    8897</tr>
    8998<tr>
    … …  
    91100<td>S_NOT_B64</td>
    92101<td>S_BREV_B32</td>
     102<td>S_BREV_B32</td>
    93103</tr>
    94104<tr>
    … …  
    96106<td>S_WQM_B32</td>
    97107<td>S_BREV_B64</td>
     108<td>S_BREV_B64</td>
    98109</tr>
    99110<tr>
    … …  
    101112<td>S_WQM_B64</td>
    102113<td>S_BCNT0_I32_B32</td>
     114<td>S_BCNT0_I32_B32</td>
    103115</tr>
    104116<tr>
    … …  
    106118<td>S_BREV_B32</td>
    107119<td>S_BCNT0_I32_B64</td>
     120<td>S_BCNT0_I32_B64</td>
    108121</tr>
    109122<tr>
    … …  
    111124<td>S_BREV_B64</td>
    112125<td>S_BCNT1_I32_B32</td>
     126<td>S_BCNT1_I32_B32</td>
    113127</tr>
    114128<tr>
    … …  
    116130<td>S_BCNT0_I32_B32</td>
    117131<td>S_BCNT1_I32_B64</td>
     132<td>S_BCNT1_I32_B64</td>
    118133</tr>
    119134<tr>
    … …  
    121136<td>S_BCNT0_I32_B64</td>
    122137<td>S_FF0_I32_B32</td>
     138<td>S_FF0_I32_B32</td>
    123139</tr>
    124140<tr>
    … …  
    126142<td>S_BCNT1_I32_B32</td>
    127143<td>S_FF0_I32_B64</td>
     144<td>S_FF0_I32_B64</td>
    128145</tr>
    129146<tr>
    … …  
    131148<td>S_BCNT1_I32_B64</td>
    132149<td>S_FF1_I32_B32</td>
     150<td>S_FF1_I32_B32</td>
    133151</tr>
    134152<tr>
    … …  
    136154<td>S_FF0_I32_B32</td>
    137155<td>S_FF1_I32_B64</td>
     156<td>S_FF1_I32_B64</td>
    138157</tr>
    139158<tr>
    … …  
    141160<td>S_FF0_I32_B64</td>
    142161<td>S_FLBIT_I32_B32</td>
     162<td>S_FLBIT_I32_B32</td>
    143163</tr>
    144164<tr>
    … …  
    146166<td>S_FF1_I32_B32</td>
    147167<td>S_FLBIT_I32_B64</td>
     168<td>S_FLBIT_I32_B64</td>
    148169</tr>
    149170<tr>
    … …  
    151172<td>S_FF1_I32_B64</td>
    152173<td>S_FLBIT_I32</td>
     174<td>S_FLBIT_I32</td>
    153175</tr>
    154176<tr>
    … …  
    156178<td>S_FLBIT_I32_B32</td>
    157179<td>S_FLBIT_I32_I64</td>
     180<td>S_FLBIT_I32_I64</td>
    158181</tr>
    159182<tr>
    … …  
    161184<td>S_FLBIT_I32_B64</td>
    162185<td>S_SEXT_I32_I8</td>
     186<td>S_SEXT_I32_I8</td>
    163187</tr>
    164188<tr>
    … …  
    166190<td>S_FLBIT_I32</td>
    167191<td>S_SEXT_I32_I16</td>
     192<td>S_SEXT_I32_I16</td>
    168193</tr>
    169194<tr>
    … …  
    171196<td>S_FLBIT_I32_I64</td>
    172197<td>S_BITSET0_B32</td>
     198<td>S_BITSET0_B32</td>
    173199</tr>
    174200<tr>
    … …  
    176202<td>S_SEXT_I32_I8</td>
    177203<td>S_BITSET0_B64</td>
     204<td>S_BITSET0_B64</td>
    178205</tr>
    179206<tr>
    … …  
    181208<td>S_SEXT_I32_I16</td>
    182209<td>S_BITSET1_B32</td>
     210<td>S_BITSET1_B32</td>
    183211</tr>
    184212<tr>
    … …  
    186214<td>S_BITSET0_B32</td>
    187215<td>S_BITSET1_B64</td>
     216<td>S_BITSET1_B64</td>
    188217</tr>
    189218<tr>
    … …  
    191220<td>S_BITSET0_B64</td>
    192221<td>S_GETPC_B64</td>
     222<td>S_GETPC_B64</td>
    193223</tr>
    194224<tr>
    … …  
    196226<td>S_BITSET1_B32</td>
    197227<td>S_SETPC_B64</td>
     228<td>S_SETPC_B64</td>
    198229</tr>
    199230<tr>
    … …  
    201232<td>S_BITSET1_B64</td>
    202233<td>S_SWAPPC_B64</td>
     234<td>S_SWAPPC_B64</td>
    203235</tr>
    204236<tr>
    … …  
    206238<td>S_GETPC_B64</td>
    207239<td>S_RFE_B64</td>
     240<td>S_RFE_B64</td>
    208241</tr>
    209242<tr>
    … …  
    211244<td>S_SETPC_B64</td>
    212245<td>S_AND_SAVEEXEC_B64</td>
     246<td>S_AND_SAVEEXEC_B64</td>
    213247</tr>
    214248<tr>
    … …  
    216250<td>S_SWAPPC_B64</td>
    217251<td>S_OR_SAVEEXEC_B64</td>
     252<td>S_OR_SAVEEXEC_B64</td>
    218253</tr>
    219254<tr>
    … …  
    221256<td>S_RFE_B64</td>
    222257<td>S_XOR_SAVEEXEC_B64</td>
     258<td>S_XOR_SAVEEXEC_B64</td>
    223259</tr>
    224260<tr>
    225261<td>35 (0x23)</td>
    226262<td>--</td>
     263<td>S_ANDN2_SAVEEXEC_B64</td>
    227264<td>S_ANDN2_SAVEEXEC_B64</td>
    228265</tr>
    … …  
    231268<td>S_AND_SAVEEXEC_B64</td>
    232269<td>S_ORN2_SAVEEXEC_B64</td>
     270<td>S_ORN2_SAVEEXEC_B64</td>
    233271</tr>
    234272<tr>
    … …  
    236274<td>S_OR_SAVEEXEC_B64</td>
    237275<td>S_NAND_SAVEEXEC_B64</td>
     276<td>S_NAND_SAVEEXEC_B64</td>
    238277</tr>
    239278<tr>
    … …  
    241280<td>S_XOR_SAVEEXEC_B64</td>
    242281<td>S_NOR_SAVEEXEC_B64</td>
     282<td>S_NOR_SAVEEXEC_B64</td>
    243283</tr>
    244284<tr>
    … …  
    246286<td>S_ANDN2_SAVEEXEC_B64</td>
    247287<td>S_XNOR_SAVEEXEC_B64</td>
     288<td>S_XNOR_SAVEEXEC_B64</td>
    248289</tr>
    249290<tr>
    … …  
    251292<td>S_ORN2_SAVEEXEC_B64</td>
    252293<td>S_QUADMASK_B32</td>
     294<td>S_QUADMASK_B32</td>
    253295</tr>
    254296<tr>
    … …  
    256298<td>S_NAND_SAVEEXEC_B64</td>
    257299<td>S_QUADMASK_B64</td>
     300<td>S_QUADMASK_B64</td>
    258301</tr>
    259302<tr>
    … …  
    261304<td>S_NOR_SAVEEXEC_B64</td>
    262305<td>S_MOVRELS_B32</td>
     306<td>S_MOVRELS_B32</td>
    263307</tr>
    264308<tr>
    … …  
    266310<td>S_XNOR_SAVEEXEC_B64</td>
    267311<td>S_MOVRELS_B64</td>
     312<td>S_MOVRELS_B64</td>
    268313</tr>
    269314<tr>
    … …  
    271316<td>S_QUADMASK_B32</td>
    272317<td>S_MOVRELD_B32</td>
     318<td>S_MOVRELD_B32</td>
    273319</tr>
    274320<tr>
    … …  
    276322<td>S_QUADMASK_B64</td>
    277323<td>S_MOVRELD_B64</td>
     324<td>S_MOVRELD_B64</td>
    278325</tr>
    279326<tr>
    … …  
    281328<td>S_MOVRELS_B32</td>
    282329<td>S_CBRANCH_JOIN</td>
     330<td>S_CBRANCH_JOIN</td>
    283331</tr>
    284332<tr>
    … …  
    286334<td>S_MOVRELS_B64</td>
    287335<td>S_MOV_REGRD_B32</td>
     336<td>S_MOV_REGRD_B32</td>
    288337</tr>
    289338<tr>
    … …  
    291340<td>S_MOVRELD_B32</td>
    292341<td>S_ABS_I32</td>
     342<td>S_ABS_I32</td>
    293343</tr>
    294344<tr>
    … …  
    296346<td>S_MOVRELD_B64</td>
    297347<td>S_MOV_FED_B32</td>
     348<td>S_MOV_FED_B32</td>
    298349</tr>
    299350<tr>
    … …  
    301352<td>S_CBRANCH_JOIN</td>
    302353<td>S_SET_GPR_IDX_IDX</td>
     354<td>S_SET_GPR_IDX_IDX</td>
    303355</tr>
    304356<tr>
    … …  
    306358<td>S_MOV_REGRD_B32</td>
    307359<td>--</td>
     360<td>S_ANDN1_SAVEEXEC_B64</td>
    308361</tr>
    309362<tr>
    … …  
    311364<td>S_ABS_I32</td>
    312365<td>--</td>
     366<td>S_ORN1_SAVEEXEC_B64</td>
    313367</tr>
    314368<tr>
    … …  
    316370<td>S_MOV_FED_B32</td>
    317371<td>--</td>
     372<td>S_ANDN1_WREXEC_B64</td>
     373</tr>
     374<tr>
     375<td>54 (0x36)</td>
     376<td>--</td>
     377<td>--</td>
     378<td>S_ANDN2_WREXEC_B64</td>
     379</tr>
     380<tr>
     381<td>55 (0x37)</td>
     382<td>--</td>
     383<td>--</td>
     384<td>S_BITREPLICATE_B64_B32</td>
    318385</tr>
    319386</tbody>
    … …  
    322389<p>Alphabetically sorted instruction list:</p>
    323390<h4>S_ABS_I32</h4>
    324 <p>Opcode: 52 (0x34) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2<br />
     391<p>Opcode: 52 (0x34) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2/1.4<br />
    325392Syntax: S_ABS_B32 SDST, SSRC0<br />
    326393Description: Store absolute signed value of the SSRC0 into SDST.
    … …  
    330397SCC = SDST!=0</code></p>
    331398<h4>S_AND_SAVEEXEC_B64</h4>
    332 <p>Opcode: 36 (0x24) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2<br />
     399<p>Opcode: 36 (0x24) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2/1.4<br />
    333400Syntax: S_AND_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    334401Description: Store EXEC register to SDST. Make bitwise AND on SSRC0 and EXEC
    … …  
    339406EXEC = SSRC0 &amp; EXEC
    340407SCC = EXEC!=0</code></p>
     408<h4>S_ANDN1_SAVEEXEC_B64</h4>
     409<p>Opcode: 51 (0x33) for GCN 1.4<br />
     410Syntax: S_ANDN2_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
     411Description: Store EXEC register to SDST. Make bitwise AND on negated SSRC0 and EXEC
     412and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     413SDST and SSRC0 are 64-bit.<br />
     414Operation:<br />
     415<code>SDST = EXEC
     416EXEC = ~SSRC0 &amp; EXEC
     417SCC = EXEC!=0</code></p>
     418<h4>S_ANDN1_WREXEC_B64</h4>
     419<p>Opcode: 53 (0x35) for GCN 1.4<br />
     420Syntax: S_ANDN1_WREXEC_B64 SDST(2), SSRC0(2)<br />
     421Description: Make bitwise AND on negated SSRC0 and EXEC
     422and store result to EXEC and SDST. If result is non-zero, store 1 to SCC,
     423otherwise store 0 to SCC. SDST and SSRC0 are 64-bit.<br />
     424Operation:<br />
     425<code>EXEC = ~SSRC0 &amp; EXEC
     426SDST = EXEC
     427SCC = EXEC!=0</code></p>
    341428<h4>S_ANDN2_SAVEEXEC_B64</h4>
    342 <p>Opcode: 39 (0x27) for GCN 1.0/1.1; 35 (0x23) for GCN 1.2<br />
     429<p>Opcode: 39 (0x27) for GCN 1.0/1.1; 35 (0x23) for GCN 1.2/1.4<br />
    343430Syntax: S_ANDN2_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    344431Description: Store EXEC register to SDST. Make bitwise AND on SSRC0 and negated EXEC
    … …  
    349436EXEC = SSRC0 &amp; ~EXEC
    350437SCC = EXEC!=0</code></p>
     438<h4>S_ANDN2_WREXEC_B64</h4>
     439<p>Opcode: 54 (0x36) for GCN 1.4<br />
     440Syntax: S_ANDN2_WREXEC_B64 SDST(2), SSRC0(2)<br />
     441Description: Make bitwise AND on SSRC0 and negated EXEC
     442and store result to EXEC and SDST. If result is non-zero, store 1 to SCC,
     443otherwise store 0 to SCC. SDST and SSRC0 are 64-bit.<br />
     444Operation:<br />
     445<code>EXEC = SSRC0 &amp; ~EXEC
     446SDST = EXEC
     447SCC = EXEC!=0</code></p>
    351448<h4>S_BCNT0_I32_B32</h4>
    352 <p>Opcode: 13 (0xd) for GCN 1.0/1.1; 10 (0xa) for GCN 1.2<br />
     449<p>Opcode: 13 (0xd) for GCN 1.0/1.1; 10 (0xa) for GCN 1.2/1.4<br />
    353450Syntax: S_BCNT0_I32_B32 SDST, SSRC0<br />
    354451Description: Count zero bits in SSRC0 and store result to SDST.
    … …  
    358455SCC = SDST!=0</code></p>
    359456<h4>S_BCNT0_I32_B64</h4>
    360 <p>Opcode: 14 (0xd) for GCN 1.0/1.1; 11 (0xb) for GCN 1.2<br />
     457<p>Opcode: 14 (0xd) for GCN 1.0/1.1; 11 (0xb) for GCN 1.2/1.4<br />
    361458Syntax: S_BCNT0_I32_B64 SDST, SSRC0(2)<br />
    362459Description: Count zero bits in SSRC0 and store result to SDST.
    … …  
    366463SCC = SDST!=0</code></p>
    367464<h4>S_BCNT1_I32_B32</h4>
    368 <p>Opcode: 15 (0xf) for GCN 1.0/1.1; 12 (0xc) for GCN 1.2<br />
     465<p>Opcode: 15 (0xf) for GCN 1.0/1.1; 12 (0xc) for GCN 1.2/1.4<br />
    369466Syntax: S_BCNT1_I32_B64 SDST, SSRC0<br />
    370467Description: Count one bits in SSRC0 and store result to SDST.
    … …  
    374471SCC = SDST!=0</code></p>
    375472<h4>S_BCNT1_I32_B64</h4>
    376 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 13 (0xd) for GCN 1.2<br />
     473<p>Opcode: 16 (0x10) for GCN 1.0/1.1; 13 (0xd) for GCN 1.2/1.4<br />
    377474Syntax: S_BCNT1_I32_B64 SDST, SSRC0(2)<br />
    378475Description: Count one bits in SSRC0 and store result to SDST.
    … …  
    381478<code>SDST = BITCOUNT(SSRC0)
    382479SCC = SDST!=0</code></p>
     480<h4>S_BITREPLICATE_B64_B32</h4>
     481<p>Opcode: 55 (0x37) for GCN 1.4<br />
     482Syntax: S_BITREPLICATE_B64_B32 SDST(2), SSRC0<br />
     483Description: Get bits from SSRC0 and doubles and store them to SDST.<br />
     484Operation:<br />
     485<code>SDST = 0
     486for (BYTE I=0; I&lt;32; I++)
     487    SDST |= (((SSRC0&gt;&gt;I)&amp;1)*3)&lt;&lt;(I&lt;&lt;1)</code></p>
    383488<h4>S_BITSET0_B32</h4>
    384 <p>Opcode: 27 (0x1b) for GCN 1.0/1.1, 24 (0x18) for GCN 1.2<br />
     489<p>Opcode: 27 (0x1b) for GCN 1.0/1.1, 24 (0x18) for GCN 1.2/1.4<br />
    385490Syntax: S_BITSET0_B32 SDST, SSRC0<br />
    386491Description: Get value from SDST, clear its bit with number specified from SSRC0, and
    … …  
    389494<code>SDST &amp;= ~(1U &lt;&lt; (SSRC0&amp;31))</code></p>
    390495<h4>S_BITSET0_B64</h4>
    391 <p>Opcode: 28 (0x1c) for GCN 1.0/1.1, 25 (0x19) for GCN 1.2<br />
     496<p>Opcode: 28 (0x1c) for GCN 1.0/1.1, 25 (0x19) for GCN 1.2/1.4<br />
    392497Syntax: S_BITSET0_B64 SDST(2), SSRC0<br />
    393498Description: Get value from SDST, clear its bit with number specified from SSRC0, and
    … …  
    396501<code>SDST &amp;= ~(1ULL &lt;&lt; (SSRC0&amp;63))</code></p>
    397502<h4>S_BITSET1_B32</h4>
    398 <p>Opcode: 29 (0x1d) for GCN 1.0/1.1, 26 (0x1a) for GCN 1.2<br />
     503<p>Opcode: 29 (0x1d) for GCN 1.0/1.1, 26 (0x1a) for GCN 1.2/1.4<br />
    399504Syntax: S_BITSET1_B32 SDST, SSRC0<br />
    400505Description: Get value from SDST, set its bit with number specified from SSRC0, and
    … …  
    403508<code>SDST |= 1U &lt;&lt; (SSRC0&amp;31)</code></p>
    404509<h4>S_BITSET1_B64</h4>
    405 <p>Opcode: 30 (0x1e) for GCN 1.0/1.1, 27 (0x1c) for GCN 1.2<br />
     510<p>Opcode: 30 (0x1e) for GCN 1.0/1.1, 27 (0x1c) for GCN 1.2/1.4<br />
    406511Syntax: S_BITSET1_B64 SDST(2), SSRC0<br />
    407512Description: Get value from SDST, set its bit with number specified from SSRC0, and
    … …  
    410515<code>SDST |= 1ULL &lt;&lt; (SSRC0&amp;63)</code></p>
    411516<h4>S_BREV_B32</h4>
    412 <p>Opcode: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2<br />
     517<p>Opcode: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2/1.4<br />
    413518Syntax: S_BREV_B32 SDST, SSRC0<br />
    414519Description: Reverse bits in SSRC0 and store result to SDST. SCC is not changed.<br />
    … …  
    416521<code>SDST = REVBIT(SSRC0)</code></p>
    417522<h4>S_BREV_B64</h4>
    418 <p>Opcode: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2<br />
     523<p>Opcode: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2/1.4<br />
    419524Syntax: S_BREV_B64 SDST(2), SSRC0(2)<br />
    420525Description: Reverse bits in SSRC0 and store result to SDST. SCC is not changed.
    … …  
    423528<code>SDST = REVBIT(SSRC0)</code></p>
    424529<h4>S_CBRANCH_JOIN</h4>
    425 <p>Opcode: 50 (0x32) for GCN 1.0/1.1; 46 (0x2e) for GCN 1.2<br />
     530<p>Opcode: 50 (0x32) for GCN 1.0/1.1; 46 (0x2e) for GCN 1.2/1.4<br />
    426531Syntax: S_CBRANCH_JOIN SSRC0<br />
    427532Description: Join conditional branch that begin from S_CBRANCH_*_FORK. If control stack
    … …  
    438543}</code></p>
    439544<h4>S_CMOV_B32</h4>
    440 <p>Opcode: 5 (0x5) for GCN 1.0/1.1; 2 (0x2) for GCN 1.2<br />
     545<p>Opcode: 5 (0x5) for GCN 1.0/1.1; 2 (0x2) for GCN 1.2/1.4<br />
    441546Syntax: S_CMOV_B32 SDST, SSRC0<br />
    442547Description: If SCC is 1, store SSRC0 into SDST, otherwise do not change SDST.
    … …  
    445550<code>SDST = SCC ? SSRC0 : SDST</code></p>
    446551<h4>S_CMOV_B64</h4>
    447 <p>Opcode: 6 (0x6) for GCN 1.0/1.1; 3 (0x3) for GCN 1.2<br />
     552<p>Opcode: 6 (0x6) for GCN 1.0/1.1; 3 (0x3) for GCN 1.2/1.4<br />
    448553Syntax: S_CMOV_B64 SDST(2), SSRC0(2)<br />
    449554Description: If SCC is 1, store SSRC0 into SDST, otherwise do not change SDST.
    … …  
    452557<code>SDST = SCC ? SSRC0 : SDST</code></p>
    453558<h4>S_FF0_I32_B32</h4>
    454 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
     559<p>Opcode: 17 (0x11) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2/1.4<br />
    455560Syntax: S_FF0_I32_B32 SDST, SSRC0<br />
    456561Description: Find first zero bit in SSRC0. If found, store number of bit to SDST,
    … …  
    462567    { SDST = i; break; }</code></p>
    463568<h4>S_FF0_I32_B64</h4>
    464 <p>Opcode: 18 (0x12) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
     569<p>Opcode: 18 (0x12) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2/1.4<br />
    465570Syntax: S_FF0_I32_B64 SDST, SSRC0(2)<br />
    466571Description: Find first zero bit in SSRC0. If found, store number of bit to SDST,
    … …  
    472577    { SDST = i; break; }</code></p>
    473578<h4>S_FF1_I32_B32</h4>
    474 <p>Opcode: 19 (0x13) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
     579<p>Opcode: 19 (0x13) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2/1.4<br />
    475580Syntax: S_FF1_I32_B32 SDST, SSRC0<br />
    476581Description: Find first one bit in SSRC0. If found, store number of bit to SDST,
    … …  
    482587    { SDST = i; break; }</code></p>
    483588<h4>S_FF1_I32_B64</h4>
    484 <p>Opcode: 20 (0x14) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2<br />
     589<p>Opcode: 20 (0x14) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2/1.4<br />
    485590Syntax: S_FF0_I32_B64 SDST, SSRC0(2)<br />
    486591Description: Find first one bit in SSRC0. If found, store number of bit to SDST,
    … …  
    492597    { SDST = i; break; }</code></p>
    493598<h4>S_FLBIT_I32_B32</h4>
    494 <p>Opcode: 21 (0x15) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2<br />
     599<p>Opcode: 21 (0x15) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2/1.4<br />
    495600Syntax: S_FLBIT_I32_B32 SDST, SSRC0<br />
    496601Description: Find last one bit in SSRC0. If found, store number of skipped bits to SDST,
    … …  
    502607    { SDST = 31-i; break; }</code></p>
    503608<h4>S_FLBIT_I32_B64</h4>
    504 <p>Opcode: 22 (0x16) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2<br />
     609<p>Opcode: 22 (0x16) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2/1.4<br />
    505610Syntax: S_FLBIT_I32_B64 SDST, SSRC0(2)<br />
    506611Description: Find last one bit in SSRC0. If found, store number of skipped bits to SDST,
    … …  
    512617    { SDST = 63-i; break; }</code></p>
    513618<h4>S_FLBIT_I32</h4>
    514 <p>Opcode: 23 (0x17) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2<br />
     619<p>Opcode: 23 (0x17) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2/1.4<br />
    515620Syntax: S_FLBIT_I32 SDST, SSRC0<br />
    516621Description: Find last opposite bit to sign in SSRC0. If found, store number of skipped bits
    … …  
    523628    { SDST = 31-i; break; }</code></p>
    524629<h4>S_FLBIT_I32_I64</h4>
    525 <p>Opcode: 24 (0x18) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br />
     630<p>Opcode: 24 (0x18) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2/1.4<br />
    526631Syntax: S_FLBIT_I32_I64 SDST, SSRC0(2)<br />
    527632Description: Find last opposite bit to sign in SSRC0. If found, store number of skipped bits
    … …  
    534639    { SDST = 63-i; break; }</code></p>
    535640<h4>S_GETPC_B64</h4>
    536 <p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />
     641<p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2/1.4<br />
    537642Syntax: S_GETPC_B64 SDST(2)<br />
    538643Description: Store program counter (PC) for next instruction to SDST. SDST is 64-bit.<br />
    … …  
    540645<code>SDST = PC + 4</code></p>
    541646<h4>S_MOV_B32</h4>
    542 <p>Opcode: 3 (0x3) for GCN 1.0/1.1; 0 (0x0) for GCN 1.2<br />
     647<p>Opcode: 3 (0x3) for GCN 1.0/1.1; 0 (0x0) for GCN 1.2/1.4<br />
    543648Syntax: S_MOV_B32 SDST, SSRC0<br />
    544649Description: Move value of SSRC0 into SDST.<br />
    … …  
    546651<code>SDST = SSRC0</code></p>
    547652<h4>S_MOV_B64</h4>
    548 <p>Opcode: 4 (0x4) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2<br />
     653<p>Opcode: 4 (0x4) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2/1.4<br />
    549654Syntax: S_MOV_B64 SDST(2), SSRC0(2)<br />
    550655Description: Move value of SSRC0 into SDST. SDST and SSRC0 are 64-bit.<br />
    … …  
    552657<code>SDST = SSRC0</code></p>
    553658<h4>S_MOVRELD_B32</h4>
    554 <p>Opcode: 48 (0x30) for GCN 1.0/1.1; 44 (0x2c) for GCN 1.2<br />
     659<p>Opcode: 48 (0x30) for GCN 1.0/1.1; 44 (0x2c) for GCN 1.2/1.4<br />
    555660Syntax: S_MOVRELD_B32 SDST, SSRC0<br />
    556661Description: Store value from SSRC0 to SGPR[SDST_NUMBER+M0 : SDST_NUMBER+M0+1].
    … …  
    559664<code>SGPR[SDST_NUMBER + M0] = SSRC0</code></p>
    560665<h4>S_MOVRELD_B64</h4>
    561 <p>Opcode: 49 (0x31) for GCN 1.0/1.1; 45 (0x2d) for GCN 1.2<br />
     666<p>Opcode: 49 (0x31) for GCN 1.0/1.1; 45 (0x2d) for GCN 1.2/1.4<br />
    562667Syntax: S_MOVRELD_B64 SDST, SSRC0<br />
    563668Description: Store value from SSRC0 to SGPR[SDST_NUMBER+M0].
    … …  
    566671<code>SGPR[SDST_NUMBER + M0 : SDST_NUMBER + M0 + 1] = SSRC0</code></p>
    567672<h4>S_MOVRELS_B32</h4>
    568 <p>Opcode: 46 (0x2e) for GCN 1.0/1.1; 42 (0x2a) for GCN 1.2<br />
     673<p>Opcode: 46 (0x2e) for GCN 1.0/1.1; 42 (0x2a) for GCN 1.2/1.4<br />
    569674Syntax: S_MOVRELS_B32 SDST, SSRC0<br />
    570675Description: Store value from SGPR[M0+SSRC0_NUMBER] to SDST.
    … …  
    573678<code>SDST = SGPR[SSRC0_NUMBER + M0]</code></p>
    574679<h4>S_MOVRELS_B64</h4>
    575 <p>Opcode: 47 (0x2f) for GCN 1.0/1.1; 43 (0x2b) for GCN 1.2<br />
     680<p>Opcode: 47 (0x2f) for GCN 1.0/1.1; 43 (0x2b) for GCN 1.2/1.4<br />
    576681Syntax: S_MOVRELS_B64 SDST(2), SSRC0(2)<br />
    577682Description: Store 64-bit value from SGPR[M0+SSRC0_NUMBER : M0+SSRC0_NUMBER+1] to SDST.
    … …  
    580685<code>SDST = SGPR[SSRC0_NUMBER + M0 : SSRC0_NUMBER + M0 + 1]</code></p>
    581686<h4>S_NAND_SAVEEXEC_B64</h4>
    582 <p>Opcode: 41 (0x29) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2<br />
     687<p>Opcode: 41 (0x29) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2/1.4<br />
    583688Syntax: S_NAND_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    584689Description: Store EXEC register to SDST. Make bitwise NAND on SSRC0 and EXEC
    … …  
    590695SCC = EXEC!=0</code></p>
    591696<h4>S_NOR_SAVEEXEC_B64</h4>
    592 <p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2<br />
     697<p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2/1.4<br />
    593698Syntax: S_NOR_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    594699Description: Store EXEC register to SDST. Make bitwise NOR on SSRC0 and EXEC
    … …  
    600705SCC = EXEC!=0</code></p>
    601706<h4>S_NOT_B32</h4>
    602 <p>Opcode: 7 (0x7) for GCN 1.0/1.1; 4 (0x4) for GCN 1.2<br />
     707<p>Opcode: 7 (0x7) for GCN 1.0/1.1; 4 (0x4) for GCN 1.2/1.4<br />
    603708Syntax: S_NOT_B32 SDST, SSRC0<br />
    604709Description: Store bitwise negation of the SSRC0 into SDST.
    … …  
    608713SCC = SDST!=0</code></p>
    609714<h4>S_NOT_B64</h4>
    610 <p>Opcode: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2<br />
     715<p>Opcode: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2/1.4<br />
    611716Syntax: S_NOT_B64 SDST(2), SSRC0(2)<br />
    612717Description: Store bitwise negation of the SSRC0 into SDST.
    … …  
    617722SCC = SDST!=0</code></p>
    618723<h4>S_OR_SAVEEXEC_B64</h4>
    619 <p>Opcode: 37 (0x25) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
     724<p>Opcode: 37 (0x25) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2/1.4<br />
    620725Syntax: S_OR_SAVEEXEC_B64 SDST(2), SDST(2)<br />
    621726Description: Store EXEC register to SDST. Make bitwise OR on SSRC0 and EXEC
    … …  
    627732SCC = EXEC!=0</code></p>
    628733<h4>S_ORN2_SAVEEXEC_B64</h4>
    629 <p>Opcode: 40 (0x28) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
     734<p>Opcode: 52 (0x34) for GCN 1.4<br />
     735Syntax: S_ORN2_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
     736Description: Store EXEC register to SDST. Make bitwise OR on negated SSRC0 and EXEC
     737and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     738SDST and SSRC0 are 64-bit.<br />
     739Operation:<br />
     740<code>SDST = EXEC
     741EXEC = ~SSRC0 &amp; EXEC
     742SCC = EXEC!=0</code></p>
     743<h4>S_ORN2_SAVEEXEC_B64</h4>
     744<p>Opcode: 40 (0x28) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2/1.4<br />
    630745Syntax: S_ORN2_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    631746Description: Store EXEC register to SDST. Make bitwise OR on SSRC0 and negated EXEC
    … …  
    637752SCC = EXEC!=0</code></p>
    638753<h4>S_QUADMASK_B32</h4>
    639 <p>Opcode: 44 (0x2c) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2<br />
     754<p>Opcode: 44 (0x2c) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2/1.4<br />
    640755Syntax: S_QUADMASK_B32 SDST, SSRC0<br />
    641756Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
    … …  
    649764SCC = SDST!=0</code></p>
    650765<h4>S_QUADMASK_B64</h4>
    651 <p>Opcode: 45 (0x2d) for GCN 1.0/1.1; 41 (0x29) for GCN 1.2<br />
     766<p>Opcode: 45 (0x2d) for GCN 1.0/1.1; 41 (0x29) for GCN 1.2/1.4<br />
    652767Syntax: S_QUADMASK_B64 SDST(2), SSRC0(2)<br />
    653768Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
    … …  
    662777SCC = SDST!=0</code></p>
    663778<h4>S_RFE_B64</h4>
    664 <p>Opcode: 34 (0x22) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
     779<p>Opcode: 34 (0x22) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2/1.4<br />
    665780Syntac: S_RFE_B64 SSRC0(2)<br />
    666781Description: Return from exception (store TTMP[0:1] to PC ???).<br />
    … …  
    668783<code>PC = TTMP[0:1]</code></p>
    669784<h4>S_SET_GPR_IDX_IDX</h4>
    670 <p>Opcode: 50 (0x32) for GCN 1.2<br />
     785<p>Opcode: 50 (0x32) for GCN 1.2/1.4<br />
    671786Syntax S_SET_GPR_IDX_IDX SSRC0(1)<br />
    672787Description: Move lowest 8 bits from SSRC0 to lowest 8 bits M0.<br />
    … …  
    674789<code>M0 = (M0 &amp; 0xffffff00) | (SSRC0 &amp; 0xff)</code></p>
    675790<h4>S_SETPC_B64</h4>
    676 <p>Opcode: 32 (0x20) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
     791<p>Opcode: 32 (0x20) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2/1.4<br />
    677792Syntax: S_SETPC_B64 SSRC0(2)<br />
    678793Description: Jump to address given SSRC0 (store SSRC0 to PC). SSRC0 is 64-bit.<br />
    … …  
    680795<code>PC = SSRC0</code></p>
    681796<h4>S_SEXT_I32_I8</h4>
    682 <p>Opcode: 25 (0x19) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2<br />
     797<p>Opcode: 25 (0x19) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2/1.4<br />
    683798Syntax: S_SEXT_I32_I8 SDST, SSRC0<br />
    684799Description: Store signed extended 8-bit value from SSRC0 to SDST.<br />
    … …  
    686801<code>SDST = SEXT((INT8)SSRC0)</code></p>
    687802<h4>S_SEXT_I32_I16</h4>
    688 <p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2<br />
     803<p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2/1.4<br />
    689804Syntax: S_SEXT_I32_I16 SDST, SSRC0<br />
    690805Description: Store signed extended 16-bit value from SSRC0 to SDST.<br />
    … …  
    692807<code>SDST = SEXT((INT16)SSRC0)</code></p>
    693808<h4>S_SWAPPC_B64</h4>
    694 <p>Opcode: 33 (0x21) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br />
     809<p>Opcode: 33 (0x21) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2/1.4<br />
    695810Syntax: S_SWAPPC_B64 SDST(2), SSRC0(2)<br />
    696811Description: Store program counter to SDST and jump to address given SSRC0
    … …  
    700815PC = SSRC0</code></p>
    701816<h4>S_WQM_B32</h4>
    702 <p>Opcode: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2<br />
     817<p>Opcode: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2/1.4<br />
    703818Syntax: S_WQM_B32 SDST, SSRC0<br />
    704819Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
    … …  
    712827SCC = SDST!=0</code></p>
    713828<h4>S_WQM_B64</h4>
    714 <p>Opcode: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2<br />
     829<p>Opcode: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2/1.4<br />
    715830Syntax: S_WQM_B64 SDST(2), SSRC0(2)<br />
    716831Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
    … …  
    725840SCC = SDST!=0</code></p>
    726841<h4>S_XNOR_SAVEEXEC_B64</h4>
    727 <p>Opcode: 43 (0x2b) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />
     842<p>Opcode: 43 (0x2b) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2/1.4<br />
    728843Syntax: S_XNOR_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    729844Description: Store EXEC register to SDST. Make bitwise XNOR on SSRC0 and EXEC
    … …  
    735850SCC = EXEC!=0</code></p>
    736851<h4>S_XOR_SAVEEXEC_B64</h4>
    737 <p>Opcode: 38 (0x26) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br />
     852<p>Opcode: 38 (0x26) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2/1.4<br />
    738853Syntax: S_XOR_SAVEEXEC_B64 SDST(2), SSRC0(2)<br />
    739854Description: Store EXEC register to SDST. Make bitwise XOR on SSRC0 and EXEC