Changes between Version 17 and Version 18 of GcnInstrsSop2


Ignore:
Timestamp:
11/23/17 21:01:18 (5 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GcnInstrsSop2

    v17 v18  
    5050<th>Mnemonic (GCN1.0/1.1)</th>
    5151<th>Mnemonic (GCN 1.2)</th>
     52<th>Mnemonic (GCN 1.4)</th>
    5253</tr>
    5354</thead>
     
    5758<td>S_ADD_U32</td>
    5859<td>S_ADD_U32</td>
     60<td>S_ADD_U32</td>
    5961</tr>
    6062<tr>
     
    6264<td>S_SUB_U32</td>
    6365<td>S_SUB_U32</td>
     66<td>S_SUB_U32</td>
    6467</tr>
    6568<tr>
     
    6770<td>S_ADD_I32</td>
    6871<td>S_ADD_I32</td>
     72<td>S_ADD_I32</td>
    6973</tr>
    7074<tr>
     
    7276<td>S_SUB_I32</td>
    7377<td>S_SUB_I32</td>
     78<td>S_SUB_I32</td>
    7479</tr>
    7580<tr>
     
    7782<td>S_ADDC_U32</td>
    7883<td>S_ADDC_U32</td>
     84<td>S_ADDC_U32</td>
    7985</tr>
    8086<tr>
     
    8288<td>S_SUBB_U32</td>
    8389<td>S_SUBB_U32</td>
     90<td>S_SUBB_U32</td>
    8491</tr>
    8592<tr>
     
    8794<td>S_MIN_I32</td>
    8895<td>S_MIN_I32</td>
     96<td>S_MIN_I32</td>
    8997</tr>
    9098<tr>
     
    92100<td>S_MIN_U32</td>
    93101<td>S_MIN_U32</td>
     102<td>S_MIN_U32</td>
    94103</tr>
    95104<tr>
     
    97106<td>S_MAX_I32</td>
    98107<td>S_MAX_I32</td>
     108<td>S_MAX_I32</td>
    99109</tr>
    100110<tr>
     
    102112<td>S_MAX_U32</td>
    103113<td>S_MAX_U32</td>
     114<td>S_MAX_U32</td>
    104115</tr>
    105116<tr>
     
    107118<td>S_CSELECT_B32</td>
    108119<td>S_CSELECT_B32</td>
     120<td>S_CSELECT_B32</td>
    109121</tr>
    110122<tr>
     
    112124<td>S_CSELECT_B64</td>
    113125<td>S_CSELECT_B64</td>
     126<td>S_CSELECT_B64</td>
    114127</tr>
    115128<tr>
     
    117130<td>--</td>
    118131<td>S_AND_B32</td>
     132<td>S_AND_B32</td>
    119133</tr>
    120134<tr>
    121135<td>13 (0xd)</td>
    122136<td>--</td>
     137<td>S_AND_B64</td>
    123138<td>S_AND_B64</td>
    124139</tr>
     
    127142<td>S_AND_B32</td>
    128143<td>S_OR_B32</td>
     144<td>S_OR_B32</td>
    129145</tr>
    130146<tr>
     
    132148<td>S_AND_B64</td>
    133149<td>S_OR_B64</td>
     150<td>S_OR_B64</td>
    134151</tr>
    135152<tr>
     
    137154<td>S_OR_B32</td>
    138155<td>S_XOR_B32</td>
     156<td>S_XOR_B32</td>
    139157</tr>
    140158<tr>
     
    142160<td>S_OR_B64</td>
    143161<td>S_XOR_B64</td>
     162<td>S_XOR_B64</td>
    144163</tr>
    145164<tr>
     
    147166<td>S_XOR_B32</td>
    148167<td>S_ANDN2_B32</td>
     168<td>S_ANDN2_B32</td>
    149169</tr>
    150170<tr>
     
    152172<td>S_XOR_B64</td>
    153173<td>S_ANDN2_B64</td>
     174<td>S_ANDN2_B64</td>
    154175</tr>
    155176<tr>
     
    157178<td>S_ANDN2_B32</td>
    158179<td>S_ORN2_B32</td>
     180<td>S_ORN2_B32</td>
    159181</tr>
    160182<tr>
     
    162184<td>S_ANDN2_B64</td>
    163185<td>S_ORN2_B64</td>
     186<td>S_ORN2_B64</td>
    164187</tr>
    165188<tr>
     
    167190<td>S_ORN2_B32</td>
    168191<td>S_NAND_B32</td>
     192<td>S_NAND_B32</td>
    169193</tr>
    170194<tr>
     
    172196<td>S_ORN2_B64</td>
    173197<td>S_NAND_B64</td>
     198<td>S_NAND_B64</td>
    174199</tr>
    175200<tr>
     
    177202<td>S_NAND_B32</td>
    178203<td>S_NOR_B32</td>
     204<td>S_NOR_B32</td>
    179205</tr>
    180206<tr>
     
    182208<td>S_NAND_B64</td>
    183209<td>S_NOR_B64</td>
     210<td>S_NOR_B64</td>
    184211</tr>
    185212<tr>
     
    187214<td>S_NOR_B32</td>
    188215<td>S_XNOR_B32</td>
     216<td>S_XNOR_B32</td>
    189217</tr>
    190218<tr>
     
    192220<td>S_NOR_B64</td>
    193221<td>S_XNOR_B64</td>
     222<td>S_XNOR_B64</td>
    194223</tr>
    195224<tr>
     
    197226<td>S_XNOR_B32</td>
    198227<td>S_LSHL_B32</td>
     228<td>S_LSHL_B32</td>
    199229</tr>
    200230<tr>
     
    202232<td>S_XNOR_B64</td>
    203233<td>S_LSHL_B64</td>
     234<td>S_LSHL_B64</td>
    204235</tr>
    205236<tr>
     
    207238<td>S_LSHL_B32</td>
    208239<td>S_LSHR_B32</td>
     240<td>S_LSHR_B32</td>
    209241</tr>
    210242<tr>
     
    212244<td>S_LSHL_B64</td>
    213245<td>S_LSHR_B64</td>
     246<td>S_LSHR_B64</td>
    214247</tr>
    215248<tr>
     
    217250<td>S_LSHR_B32</td>
    218251<td>S_ASHR_I32</td>
     252<td>S_ASHR_I32</td>
    219253</tr>
    220254<tr>
     
    222256<td>S_LSHR_B64</td>
    223257<td>S_ASHR_I64</td>
     258<td>S_ASHR_I64</td>
    224259</tr>
    225260<tr>
     
    227262<td>S_ASHR_I32</td>
    228263<td>S_BFM_B32</td>
     264<td>S_BFM_B32</td>
    229265</tr>
    230266<tr>
     
    232268<td>S_ASHR_I64</td>
    233269<td>S_BFM_B64</td>
     270<td>S_BFM_B64</td>
    234271</tr>
    235272<tr>
     
    237274<td>S_BFM_B32</td>
    238275<td>S_MUL_I32</td>
     276<td>S_MUL_I32</td>
    239277</tr>
    240278<tr>
     
    242280<td>S_BFM_B64</td>
    243281<td>S_BFE_U32</td>
     282<td>S_BFE_U32</td>
    244283</tr>
    245284<tr>
     
    247286<td>S_MUL_I32</td>
    248287<td>S_BFE_I32</td>
     288<td>S_BFE_I32</td>
    249289</tr>
    250290<tr>
     
    252292<td>S_BFE_U32</td>
    253293<td>S_BFE_U64</td>
     294<td>S_BFE_U64</td>
    254295</tr>
    255296<tr>
     
    257298<td>S_BFE_I32</td>
    258299<td>S_BFE_I64</td>
     300<td>S_BFE_I64</td>
    259301</tr>
    260302<tr>
     
    262304<td>S_BFE_U64</td>
    263305<td>S_CBRANCH_G_FORK</td>
     306<td>S_CBRANCH_G_FORK</td>
    264307</tr>
    265308<tr>
     
    267310<td>S_BFE_I64</td>
    268311<td>S_ABSDIFF_I32</td>
     312<td>S_ABSDIFF_I32</td>
    269313</tr>
    270314<tr>
     
    272316<td>S_CBRANCH_G_FORK</td>
    273317<td>S_RFE_RESTORE_B64</td>
     318<td>S_RFE_RESTORE_B64</td>
    274319</tr>
    275320<tr>
     
    277322<td>S_ABSDIFF_I32</td>
    278323<td>--</td>
     324<td>S_MUL_HI_U32</td>
     325</tr>
     326<tr>
     327<td>45 (0x2d)</td>
     328<td>--</td>
     329<td>--</td>
     330<td>S_MUL_HI_I32</td>
     331</tr>
     332<tr>
     333<td>46 (0x2e)</td>
     334<td>--</td>
     335<td>--</td>
     336<td>S_LSHL1_ADD_U32</td>
     337</tr>
     338<tr>
     339<td>47 (0x2f)</td>
     340<td>--</td>
     341<td>--</td>
     342<td>S_LSHL2_ADD_U32</td>
     343</tr>
     344<tr>
     345<td>48 (0x30)</td>
     346<td>--</td>
     347<td>--</td>
     348<td>S_LSHL3_ADD_U32</td>
     349</tr>
     350<tr>
     351<td>49 (0x31)</td>
     352<td>--</td>
     353<td>--</td>
     354<td>S_LSHL4_ADD_U32</td>
     355</tr>
     356<tr>
     357<td>50 (0x32)</td>
     358<td>--</td>
     359<td>--</td>
     360<td>S_PACK_LL_B32_B16</td>
     361</tr>
     362<tr>
     363<td>51 (0x33)</td>
     364<td>--</td>
     365<td>--</td>
     366<td>S_PACK_LH_B32_B16</td>
     367</tr>
     368<tr>
     369<td>52 (0x34)</td>
     370<td>--</td>
     371<td>--</td>
     372<td>S_PACK_HH_B32_B16</td>
    279373</tr>
    280374</tbody>
     
    488582<code>SDST = SCC ? SSRC0 : SSRC1</code></p>
    489583<h4>S_LSHL_B32</h4>
    490 <p>Opcode: 30 (0x1e) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />
     584<p>Opcode: 30 (0x1e) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2/1.4<br />
    491585Syntax: S_LSHL_B32 SDST, SSRC0, SSRC1<br />
    492586Description: Shift left SSRC0 by (SSRC1&amp;31) bits and store result into SDST.
     
    496590SCC = SDST!=0</code></p>
    497591<h4>S_LSHL_B64</h4>
    498 <p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
     592<p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2/1.4<br />
    499593Syntax: S_LSHL_B64 SDST(2), SSRC0(2), SSRC1<br />
    500594Description: Shift left SSRC0 by (SSRC1&amp;63) bits and store result into SDST.
     
    504598<code>SDST = SSRC0 &lt;&lt; (SSRC1 &amp; 63)
    505599SCC = SDST!=0</code></p>
     600<h4>S_LSHL1_ADD_U32</h4>
     601<p>Opcode: 46 (0x2e) for GCN 1.4<br />
     602Syntax: S_LSHL1_ADD_U32 SDST, SRC0, SRC1<br />
     603Description: Shift left SSRC0 by 1 bits and adds this result to SSRC1 and store final
     604result into SDST. If final value is greater than maximal value of 32-bit type then store
     6051 to SCC, otherwise store 0 to SCC.<br />
     606Operation:<br />
     607<code>UINT64 TMP = (SSRC0&lt;&lt;1) + SSRC1
     608SDST = TMP&amp;0xffffffff
     609SCC = TMP &gt;= (1ULL&lt;&lt;32)</code></p>
     610<h4>S_LSHL2_ADD_U32</h4>
     611<p>Opcode: 47 (0x2f) for GCN 1.4<br />
     612Syntax: S_LSHL2_ADD_U32 SDST, SRC0, SRC1<br />
     613Description: Shift left SSRC0 by 2 bits and adds this result to SSRC1 and store final
     614result into SDST. If final value is greater than maximal value of 32-bit type then store
     6151 to SCC, otherwise store 0 to SCC.<br />
     616Operation:<br />
     617<code>UINT64 TMP = (SSRC0&lt;&lt;2) + SSRC1
     618SDST = TMP&amp;0xffffffff
     619SCC = TMP &gt;= (1ULL&lt;&lt;32)</code></p>
     620<h4>S_LSHL3_ADD_U32</h4>
     621<p>Opcode: 48 (0x30) for GCN 1.4<br />
     622Syntax: S_LSHL3_ADD_U32 SDST, SRC0, SRC1<br />
     623Description: Shift left SSRC0 by 3 bits and adds this result to SSRC1 and store final
     624result into SDST. If final value is greater than maximal value of 32-bit type then store
     6251 to SCC, otherwise store 0 to SCC.<br />
     626Operation:<br />
     627<code>UINT64 TMP = (SSRC0&lt;&lt;3) + SSRC1
     628SDST = TMP&amp;0xffffffff
     629SCC = TMP &gt;= (1ULL&lt;&lt;32)</code></p>
     630<h4>S_LSHL4_ADD_U32</h4>
     631<p>Opcode: 49 (0x31) for GCN 1.4<br />
     632Syntax: S_LSHL4_ADD_U32 SDST, SRC0, SRC1<br />
     633Description: Shift left SSRC0 by 4 bits and adds this result to SSRC1 and store final
     634result into SDST. If final value is greater than maximal value of 32-bit type then store
     6351 to SCC, otherwise store 0 to SCC.<br />
     636Operation:<br />
     637<code>UINT64 TMP = (SSRC0&lt;&lt;4) + SSRC1
     638SDST = TMP&amp;0xffffffff
     639SCC = TMP &gt;= (1ULL&lt;&lt;32)</code></p>
    506640<h4>S_LSHR_B32</h4>
    507 <p>Opcode: 32 (0x20) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br />
     641<p>Opcode: 32 (0x20) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2/1.4<br />
    508642Syntax: S_LSHR_B32 SDST, SSRC0, SSRC1<br />
    509643Description: Shift right SSRC0 by (SSRC1&amp;31) bits and store result into SDST.
     
    513647SCC = SDST!=0</code></p>
    514648<h4>S_LSHR_B64</h4>
    515 <p>Opcode: 33 (0x21) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
     649<p>Opcode: 33 (0x21) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2/1.4<br />
    516650Syntax: S_LSHR_B64 SDST(2), SSRC0(2), SSRC1<br />
    517651Description: Shift right SSRC0 by (SSRC1&amp;63) bits and store result into SDST.
     
    553687<code>SDST = MIN(SSRC0, SSRC1)
    554688SCC = SSRC0 &lt; SSRC1</code></p>
     689<h4>S_MUL_HI_I32</h4>
     690<p>Opcode: 45 (0x2d) for GCN 1.4<br />
     691Syntax: S_MUL_HI_I32 SDST, SSRC0, SSRC1<br />
     692Description: Multiply signed values of SSRC0 and SSRC1 and store high 32 bits of
     693signed result into SDST. Do no change SCC.<br />
     694Operation:<br />
     695<code>SDST = ((INT64)SSRC0 * (INT32)SSRC1)&gt;&gt;32</code></p>
     696<h4>S_MUL_HI_U32</h4>
     697<p>Opcode: 44 (0x2c) for GCN 1.4<br />
     698Syntax: S_MUL_HI_U32 SDST, SSRC0, SSRC1<br />
     699Description: Multiply unsigned values of SSRC0 and SSRC1 and store high 32 bits of
     700unsigned result into SDST. Do no change SCC.<br />
     701Operation:<br />
     702<code>SDST = ((UINT64)SSRC0 * SSRC1)&gt;&gt;32</code></p>
    555703<h4>S_MUL_I32</h4>
    556 <p>Opcode: 38 (0x26) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
    557 Syntax: S_MUL_I32 SDST, SSRC0, SSRC1
     704<p>Opcode: 38 (0x26) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2/1.4<br />
     705Syntax: S_MUL_I32 SDST, SSRC0, SSRC1<br />
    558706Description: Multiply SSRC0 and SSRC1 and store result into SDST. Do not change SCC.<br />
    559707Operation:<br />
    560708<code>SDST = SSRC0 * SSRC1</code></p>
    561709<h4>S_NAND_B32</h4>
    562 <p>Opcode: 24 (0x18) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2<br />
     710<p>Opcode: 24 (0x18) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2/1.4<br />
    563711Syntax: S_NAND_B32 SDST, SSRC0, SSRC1<br />
    564712Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    568716SCC = SDST!=0</code></p>
    569717<h4>S_NAND_B64</h4>
    570 <p>Opcode: 25 (0x19) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2<br />
     718<p>Opcode: 25 (0x19) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2/1.4<br />
    571719Syntax: S_NAND_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    572720Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    576724SCC = SDST!=0</code></p>
    577725<h4>S_NOR_B32</h4>
    578 <p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2<br />
     726<p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2/1.4<br />
    579727Syntax: S_NOR_B32 SDST, SSRC0, SSRC1<br />
    580728Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    584732SCC = SDST!=0</code></p>
    585733<h4>S_NOR_B64</h4>
    586 <p>Opcode: 27 (0x1b) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2<br />
     734<p>Opcode: 27 (0x1b) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2/1.4<br />
    587735Syntax: S_NOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    588736Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    592740SCC = SDST!=0</code></p>
    593741<h4>S_OR_B32</h4>
    594 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
     742<p>Opcode: 16 (0x10) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2/1.4<br />
    595743Syntax: S_OR_B32 SDST, SSRC0, SSRC1<br />
    596744Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    600748SCC = SDST!=0</code></p>
    601749<h4>S_OR_B64</h4>
    602 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
     750<p>Opcode: 17 (0x11) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2/1.4<br />
    603751Syntax: S_OR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    604752Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    608756SCC = SDST!=0</code></p>
    609757<h4>S_ORN2_B32</h4>
    610 <p>Opcode: 22 (0x16) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2<br />
     758<p>Opcode: 22 (0x16) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2/1.4<br />
    611759Syntax: S_ORN2_B32 SDST, SSRC0, SSRC1<br />
    612760Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST,
     
    616764SCC = SDST!=0</code></p>
    617765<h4>S_ORN2_B64</h4>
    618 <p>Opcode: 23 (0x17) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br />
     766<p>Opcode: 23 (0x17) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2/1.4<br />
    619767Syntax: S_ORN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    620768Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST,
     
    624772<code>SDST = SSRC0 | ~SSRC1
    625773SCC = SDST!=0</code></p>
     774<h4>S_PACK_HH_B32_B16</h4>
     775<p>Opcode: 52 (0x34) for GCN 1.4<br />
     776Syntax: S_PACK_HH_B32_B16 SDST, SSRC0, SSRC1<br />
     777Description: Get last 16 bits from SSRC0 and store in first 16 bits in SDST,
     778Get last 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br />
     779Operation:<br />
     780<code>SDST = (SSRC0&gt;&gt;16) | (SSRC1&amp;0xffff0000)</code></p>
     781<h4>S_PACK_LH_B32_B16</h4>
     782<p>Opcode: 51 (0x33) for GCN 1.4<br />
     783Syntax: S_PACK_LH_B32_B16 SDST, SSRC0, SSRC1<br />
     784Description: Get first 16 bits from SSRC0 and store in first 16 bits in SDST,
     785Get last 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br />
     786Operation:<br />
     787<code>SDST = (SSRC0&amp;0xffff) | (SSRC1&amp;0xffff0000)</code></p>
     788<h4>S_PACK_LL_B32_B16</h4>
     789<p>Opcode: 50 (0x32) for GCN 1.4<br />
     790Syntax: S_PACK_LL_B32_B16 SDST, SSRC0, SSRC1<br />
     791Description: Get first 16 bits from SSRC0 and store in first 16 bits in SDST,
     792Get first 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br />
     793Operation:<br />
     794<code>SDST = (SSRC0&amp;0xffff) | ((SSRC1&amp;0xffff)&lt;&lt;16)</code></p>
    626795<h4>S_RFE_RESTORE_B64</h4>
    627 <p>Opcode: 43 (0x2b) for GCN 1.2<br />
     796<p>Opcode: 43 (0x2b) for GCN 1.2/1.4<br />
    628797Syntax: S_RFE_RESTORE_B64 SDST(2), SSRC0(1)<br />
    629798Description: Return from exception handler and set: INST_ATC = SSRC1.U32[0] ???</p>
     
    657826SCC = (temp&gt;&gt;32)!=0</code></p>
    658827<h4>S_XNOR_B32</h4>
    659 <p>Opcode: 28 (0x1c) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2<br />
     828<p>Opcode: 28 (0x1c) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2/1.4<br />
    660829Syntax: S_XNOR_B32 SDST, SSRC0, SSRC1<br />
    661830Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    665834SCC = SDST!=0</code></p>
    666835<h4>S_XNOR_B64</h4>
    667 <p>Opcode: 29 (0x1d) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2<br />
     836<p>Opcode: 29 (0x1d) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2/1.4<br />
    668837Syntax: S_XNOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    669838Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    673842SCC = SDST!=0</code></p>
    674843<h4>S_XOR_B32</h4>
    675 <p>Opcode: 18 (0x12) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
     844<p>Opcode: 18 (0x12) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2/1.4<br />
    676845Syntax: S_XOR_B32 SDST, SSRC0, SSRC1<br />
    677846Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store
     
    681850SCC = SDST!=0</code></p>
    682851<h4>S_XOR_B64</h4>
    683 <p>Opcode: 19 (0x13) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2<br />
     852<p>Opcode: 19 (0x13) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2/1.4<br />
    684853Syntax: S_XOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    685854Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store