Changes between Version 17 and Version 18 of GcnInstrsSop2
- Timestamp:
- 11/23/17 21:01:18 (6 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
GcnInstrsSop2
v17 v18 50 50 <th>Mnemonic (GCN1.0/1.1)</th> 51 51 <th>Mnemonic (GCN 1.2)</th> 52 <th>Mnemonic (GCN 1.4)</th> 52 53 </tr> 53 54 </thead> … … 57 58 <td>S_ADD_U32</td> 58 59 <td>S_ADD_U32</td> 60 <td>S_ADD_U32</td> 59 61 </tr> 60 62 <tr> … … 62 64 <td>S_SUB_U32</td> 63 65 <td>S_SUB_U32</td> 66 <td>S_SUB_U32</td> 64 67 </tr> 65 68 <tr> … … 67 70 <td>S_ADD_I32</td> 68 71 <td>S_ADD_I32</td> 72 <td>S_ADD_I32</td> 69 73 </tr> 70 74 <tr> … … 72 76 <td>S_SUB_I32</td> 73 77 <td>S_SUB_I32</td> 78 <td>S_SUB_I32</td> 74 79 </tr> 75 80 <tr> … … 77 82 <td>S_ADDC_U32</td> 78 83 <td>S_ADDC_U32</td> 84 <td>S_ADDC_U32</td> 79 85 </tr> 80 86 <tr> … … 82 88 <td>S_SUBB_U32</td> 83 89 <td>S_SUBB_U32</td> 90 <td>S_SUBB_U32</td> 84 91 </tr> 85 92 <tr> … … 87 94 <td>S_MIN_I32</td> 88 95 <td>S_MIN_I32</td> 96 <td>S_MIN_I32</td> 89 97 </tr> 90 98 <tr> … … 92 100 <td>S_MIN_U32</td> 93 101 <td>S_MIN_U32</td> 102 <td>S_MIN_U32</td> 94 103 </tr> 95 104 <tr> … … 97 106 <td>S_MAX_I32</td> 98 107 <td>S_MAX_I32</td> 108 <td>S_MAX_I32</td> 99 109 </tr> 100 110 <tr> … … 102 112 <td>S_MAX_U32</td> 103 113 <td>S_MAX_U32</td> 114 <td>S_MAX_U32</td> 104 115 </tr> 105 116 <tr> … … 107 118 <td>S_CSELECT_B32</td> 108 119 <td>S_CSELECT_B32</td> 120 <td>S_CSELECT_B32</td> 109 121 </tr> 110 122 <tr> … … 112 124 <td>S_CSELECT_B64</td> 113 125 <td>S_CSELECT_B64</td> 126 <td>S_CSELECT_B64</td> 114 127 </tr> 115 128 <tr> … … 117 130 <td>--</td> 118 131 <td>S_AND_B32</td> 132 <td>S_AND_B32</td> 119 133 </tr> 120 134 <tr> 121 135 <td>13 (0xd)</td> 122 136 <td>--</td> 137 <td>S_AND_B64</td> 123 138 <td>S_AND_B64</td> 124 139 </tr> … … 127 142 <td>S_AND_B32</td> 128 143 <td>S_OR_B32</td> 144 <td>S_OR_B32</td> 129 145 </tr> 130 146 <tr> … … 132 148 <td>S_AND_B64</td> 133 149 <td>S_OR_B64</td> 150 <td>S_OR_B64</td> 134 151 </tr> 135 152 <tr> … … 137 154 <td>S_OR_B32</td> 138 155 <td>S_XOR_B32</td> 156 <td>S_XOR_B32</td> 139 157 </tr> 140 158 <tr> … … 142 160 <td>S_OR_B64</td> 143 161 <td>S_XOR_B64</td> 162 <td>S_XOR_B64</td> 144 163 </tr> 145 164 <tr> … … 147 166 <td>S_XOR_B32</td> 148 167 <td>S_ANDN2_B32</td> 168 <td>S_ANDN2_B32</td> 149 169 </tr> 150 170 <tr> … … 152 172 <td>S_XOR_B64</td> 153 173 <td>S_ANDN2_B64</td> 174 <td>S_ANDN2_B64</td> 154 175 </tr> 155 176 <tr> … … 157 178 <td>S_ANDN2_B32</td> 158 179 <td>S_ORN2_B32</td> 180 <td>S_ORN2_B32</td> 159 181 </tr> 160 182 <tr> … … 162 184 <td>S_ANDN2_B64</td> 163 185 <td>S_ORN2_B64</td> 186 <td>S_ORN2_B64</td> 164 187 </tr> 165 188 <tr> … … 167 190 <td>S_ORN2_B32</td> 168 191 <td>S_NAND_B32</td> 192 <td>S_NAND_B32</td> 169 193 </tr> 170 194 <tr> … … 172 196 <td>S_ORN2_B64</td> 173 197 <td>S_NAND_B64</td> 198 <td>S_NAND_B64</td> 174 199 </tr> 175 200 <tr> … … 177 202 <td>S_NAND_B32</td> 178 203 <td>S_NOR_B32</td> 204 <td>S_NOR_B32</td> 179 205 </tr> 180 206 <tr> … … 182 208 <td>S_NAND_B64</td> 183 209 <td>S_NOR_B64</td> 210 <td>S_NOR_B64</td> 184 211 </tr> 185 212 <tr> … … 187 214 <td>S_NOR_B32</td> 188 215 <td>S_XNOR_B32</td> 216 <td>S_XNOR_B32</td> 189 217 </tr> 190 218 <tr> … … 192 220 <td>S_NOR_B64</td> 193 221 <td>S_XNOR_B64</td> 222 <td>S_XNOR_B64</td> 194 223 </tr> 195 224 <tr> … … 197 226 <td>S_XNOR_B32</td> 198 227 <td>S_LSHL_B32</td> 228 <td>S_LSHL_B32</td> 199 229 </tr> 200 230 <tr> … … 202 232 <td>S_XNOR_B64</td> 203 233 <td>S_LSHL_B64</td> 234 <td>S_LSHL_B64</td> 204 235 </tr> 205 236 <tr> … … 207 238 <td>S_LSHL_B32</td> 208 239 <td>S_LSHR_B32</td> 240 <td>S_LSHR_B32</td> 209 241 </tr> 210 242 <tr> … … 212 244 <td>S_LSHL_B64</td> 213 245 <td>S_LSHR_B64</td> 246 <td>S_LSHR_B64</td> 214 247 </tr> 215 248 <tr> … … 217 250 <td>S_LSHR_B32</td> 218 251 <td>S_ASHR_I32</td> 252 <td>S_ASHR_I32</td> 219 253 </tr> 220 254 <tr> … … 222 256 <td>S_LSHR_B64</td> 223 257 <td>S_ASHR_I64</td> 258 <td>S_ASHR_I64</td> 224 259 </tr> 225 260 <tr> … … 227 262 <td>S_ASHR_I32</td> 228 263 <td>S_BFM_B32</td> 264 <td>S_BFM_B32</td> 229 265 </tr> 230 266 <tr> … … 232 268 <td>S_ASHR_I64</td> 233 269 <td>S_BFM_B64</td> 270 <td>S_BFM_B64</td> 234 271 </tr> 235 272 <tr> … … 237 274 <td>S_BFM_B32</td> 238 275 <td>S_MUL_I32</td> 276 <td>S_MUL_I32</td> 239 277 </tr> 240 278 <tr> … … 242 280 <td>S_BFM_B64</td> 243 281 <td>S_BFE_U32</td> 282 <td>S_BFE_U32</td> 244 283 </tr> 245 284 <tr> … … 247 286 <td>S_MUL_I32</td> 248 287 <td>S_BFE_I32</td> 288 <td>S_BFE_I32</td> 249 289 </tr> 250 290 <tr> … … 252 292 <td>S_BFE_U32</td> 253 293 <td>S_BFE_U64</td> 294 <td>S_BFE_U64</td> 254 295 </tr> 255 296 <tr> … … 257 298 <td>S_BFE_I32</td> 258 299 <td>S_BFE_I64</td> 300 <td>S_BFE_I64</td> 259 301 </tr> 260 302 <tr> … … 262 304 <td>S_BFE_U64</td> 263 305 <td>S_CBRANCH_G_FORK</td> 306 <td>S_CBRANCH_G_FORK</td> 264 307 </tr> 265 308 <tr> … … 267 310 <td>S_BFE_I64</td> 268 311 <td>S_ABSDIFF_I32</td> 312 <td>S_ABSDIFF_I32</td> 269 313 </tr> 270 314 <tr> … … 272 316 <td>S_CBRANCH_G_FORK</td> 273 317 <td>S_RFE_RESTORE_B64</td> 318 <td>S_RFE_RESTORE_B64</td> 274 319 </tr> 275 320 <tr> … … 277 322 <td>S_ABSDIFF_I32</td> 278 323 <td>--</td> 324 <td>S_MUL_HI_U32</td> 325 </tr> 326 <tr> 327 <td>45 (0x2d)</td> 328 <td>--</td> 329 <td>--</td> 330 <td>S_MUL_HI_I32</td> 331 </tr> 332 <tr> 333 <td>46 (0x2e)</td> 334 <td>--</td> 335 <td>--</td> 336 <td>S_LSHL1_ADD_U32</td> 337 </tr> 338 <tr> 339 <td>47 (0x2f)</td> 340 <td>--</td> 341 <td>--</td> 342 <td>S_LSHL2_ADD_U32</td> 343 </tr> 344 <tr> 345 <td>48 (0x30)</td> 346 <td>--</td> 347 <td>--</td> 348 <td>S_LSHL3_ADD_U32</td> 349 </tr> 350 <tr> 351 <td>49 (0x31)</td> 352 <td>--</td> 353 <td>--</td> 354 <td>S_LSHL4_ADD_U32</td> 355 </tr> 356 <tr> 357 <td>50 (0x32)</td> 358 <td>--</td> 359 <td>--</td> 360 <td>S_PACK_LL_B32_B16</td> 361 </tr> 362 <tr> 363 <td>51 (0x33)</td> 364 <td>--</td> 365 <td>--</td> 366 <td>S_PACK_LH_B32_B16</td> 367 </tr> 368 <tr> 369 <td>52 (0x34)</td> 370 <td>--</td> 371 <td>--</td> 372 <td>S_PACK_HH_B32_B16</td> 279 373 </tr> 280 374 </tbody> … … 488 582 <code>SDST = SCC ? SSRC0 : SSRC1</code></p> 489 583 <h4>S_LSHL_B32</h4> 490 <p>Opcode: 30 (0x1e) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2 <br />584 <p>Opcode: 30 (0x1e) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2/1.4<br /> 491 585 Syntax: S_LSHL_B32 SDST, SSRC0, SSRC1<br /> 492 586 Description: Shift left SSRC0 by (SSRC1&31) bits and store result into SDST. … … 496 590 SCC = SDST!=0</code></p> 497 591 <h4>S_LSHL_B64</h4> 498 <p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2 <br />592 <p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2/1.4<br /> 499 593 Syntax: S_LSHL_B64 SDST(2), SSRC0(2), SSRC1<br /> 500 594 Description: Shift left SSRC0 by (SSRC1&63) bits and store result into SDST. … … 504 598 <code>SDST = SSRC0 << (SSRC1 & 63) 505 599 SCC = SDST!=0</code></p> 600 <h4>S_LSHL1_ADD_U32</h4> 601 <p>Opcode: 46 (0x2e) for GCN 1.4<br /> 602 Syntax: S_LSHL1_ADD_U32 SDST, SRC0, SRC1<br /> 603 Description: Shift left SSRC0 by 1 bits and adds this result to SSRC1 and store final 604 result into SDST. If final value is greater than maximal value of 32-bit type then store 605 1 to SCC, otherwise store 0 to SCC.<br /> 606 Operation:<br /> 607 <code>UINT64 TMP = (SSRC0<<1) + SSRC1 608 SDST = TMP&0xffffffff 609 SCC = TMP >= (1ULL<<32)</code></p> 610 <h4>S_LSHL2_ADD_U32</h4> 611 <p>Opcode: 47 (0x2f) for GCN 1.4<br /> 612 Syntax: S_LSHL2_ADD_U32 SDST, SRC0, SRC1<br /> 613 Description: Shift left SSRC0 by 2 bits and adds this result to SSRC1 and store final 614 result into SDST. If final value is greater than maximal value of 32-bit type then store 615 1 to SCC, otherwise store 0 to SCC.<br /> 616 Operation:<br /> 617 <code>UINT64 TMP = (SSRC0<<2) + SSRC1 618 SDST = TMP&0xffffffff 619 SCC = TMP >= (1ULL<<32)</code></p> 620 <h4>S_LSHL3_ADD_U32</h4> 621 <p>Opcode: 48 (0x30) for GCN 1.4<br /> 622 Syntax: S_LSHL3_ADD_U32 SDST, SRC0, SRC1<br /> 623 Description: Shift left SSRC0 by 3 bits and adds this result to SSRC1 and store final 624 result into SDST. If final value is greater than maximal value of 32-bit type then store 625 1 to SCC, otherwise store 0 to SCC.<br /> 626 Operation:<br /> 627 <code>UINT64 TMP = (SSRC0<<3) + SSRC1 628 SDST = TMP&0xffffffff 629 SCC = TMP >= (1ULL<<32)</code></p> 630 <h4>S_LSHL4_ADD_U32</h4> 631 <p>Opcode: 49 (0x31) for GCN 1.4<br /> 632 Syntax: S_LSHL4_ADD_U32 SDST, SRC0, SRC1<br /> 633 Description: Shift left SSRC0 by 4 bits and adds this result to SSRC1 and store final 634 result into SDST. If final value is greater than maximal value of 32-bit type then store 635 1 to SCC, otherwise store 0 to SCC.<br /> 636 Operation:<br /> 637 <code>UINT64 TMP = (SSRC0<<4) + SSRC1 638 SDST = TMP&0xffffffff 639 SCC = TMP >= (1ULL<<32)</code></p> 506 640 <h4>S_LSHR_B32</h4> 507 <p>Opcode: 32 (0x20) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2 <br />641 <p>Opcode: 32 (0x20) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2/1.4<br /> 508 642 Syntax: S_LSHR_B32 SDST, SSRC0, SSRC1<br /> 509 643 Description: Shift right SSRC0 by (SSRC1&31) bits and store result into SDST. … … 513 647 SCC = SDST!=0</code></p> 514 648 <h4>S_LSHR_B64</h4> 515 <p>Opcode: 33 (0x21) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2 <br />649 <p>Opcode: 33 (0x21) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2/1.4<br /> 516 650 Syntax: S_LSHR_B64 SDST(2), SSRC0(2), SSRC1<br /> 517 651 Description: Shift right SSRC0 by (SSRC1&63) bits and store result into SDST. … … 553 687 <code>SDST = MIN(SSRC0, SSRC1) 554 688 SCC = SSRC0 < SSRC1</code></p> 689 <h4>S_MUL_HI_I32</h4> 690 <p>Opcode: 45 (0x2d) for GCN 1.4<br /> 691 Syntax: S_MUL_HI_I32 SDST, SSRC0, SSRC1<br /> 692 Description: Multiply signed values of SSRC0 and SSRC1 and store high 32 bits of 693 signed result into SDST. Do no change SCC.<br /> 694 Operation:<br /> 695 <code>SDST = ((INT64)SSRC0 * (INT32)SSRC1)>>32</code></p> 696 <h4>S_MUL_HI_U32</h4> 697 <p>Opcode: 44 (0x2c) for GCN 1.4<br /> 698 Syntax: S_MUL_HI_U32 SDST, SSRC0, SSRC1<br /> 699 Description: Multiply unsigned values of SSRC0 and SSRC1 and store high 32 bits of 700 unsigned result into SDST. Do no change SCC.<br /> 701 Operation:<br /> 702 <code>SDST = ((UINT64)SSRC0 * SSRC1)>>32</code></p> 555 703 <h4>S_MUL_I32</h4> 556 <p>Opcode: 38 (0x26) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2 <br />557 Syntax: S_MUL_I32 SDST, SSRC0, SSRC1 704 <p>Opcode: 38 (0x26) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2/1.4<br /> 705 Syntax: S_MUL_I32 SDST, SSRC0, SSRC1<br /> 558 706 Description: Multiply SSRC0 and SSRC1 and store result into SDST. Do not change SCC.<br /> 559 707 Operation:<br /> 560 708 <code>SDST = SSRC0 * SSRC1</code></p> 561 709 <h4>S_NAND_B32</h4> 562 <p>Opcode: 24 (0x18) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2 <br />710 <p>Opcode: 24 (0x18) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2/1.4<br /> 563 711 Syntax: S_NAND_B32 SDST, SSRC0, SSRC1<br /> 564 712 Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store … … 568 716 SCC = SDST!=0</code></p> 569 717 <h4>S_NAND_B64</h4> 570 <p>Opcode: 25 (0x19) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2 <br />718 <p>Opcode: 25 (0x19) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2/1.4<br /> 571 719 Syntax: S_NAND_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 572 720 Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store … … 576 724 SCC = SDST!=0</code></p> 577 725 <h4>S_NOR_B32</h4> 578 <p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2 <br />726 <p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2/1.4<br /> 579 727 Syntax: S_NOR_B32 SDST, SSRC0, SSRC1<br /> 580 728 Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 584 732 SCC = SDST!=0</code></p> 585 733 <h4>S_NOR_B64</h4> 586 <p>Opcode: 27 (0x1b) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2 <br />734 <p>Opcode: 27 (0x1b) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2/1.4<br /> 587 735 Syntax: S_NOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 588 736 Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 592 740 SCC = SDST!=0</code></p> 593 741 <h4>S_OR_B32</h4> 594 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2 <br />742 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2/1.4<br /> 595 743 Syntax: S_OR_B32 SDST, SSRC0, SSRC1<br /> 596 744 Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 600 748 SCC = SDST!=0</code></p> 601 749 <h4>S_OR_B64</h4> 602 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2 <br />750 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2/1.4<br /> 603 751 Syntax: S_OR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 604 752 Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 608 756 SCC = SDST!=0</code></p> 609 757 <h4>S_ORN2_B32</h4> 610 <p>Opcode: 22 (0x16) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2 <br />758 <p>Opcode: 22 (0x16) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2/1.4<br /> 611 759 Syntax: S_ORN2_B32 SDST, SSRC0, SSRC1<br /> 612 760 Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST, … … 616 764 SCC = SDST!=0</code></p> 617 765 <h4>S_ORN2_B64</h4> 618 <p>Opcode: 23 (0x17) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2 <br />766 <p>Opcode: 23 (0x17) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2/1.4<br /> 619 767 Syntax: S_ORN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 620 768 Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST, … … 624 772 <code>SDST = SSRC0 | ~SSRC1 625 773 SCC = SDST!=0</code></p> 774 <h4>S_PACK_HH_B32_B16</h4> 775 <p>Opcode: 52 (0x34) for GCN 1.4<br /> 776 Syntax: S_PACK_HH_B32_B16 SDST, SSRC0, SSRC1<br /> 777 Description: Get last 16 bits from SSRC0 and store in first 16 bits in SDST, 778 Get last 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br /> 779 Operation:<br /> 780 <code>SDST = (SSRC0>>16) | (SSRC1&0xffff0000)</code></p> 781 <h4>S_PACK_LH_B32_B16</h4> 782 <p>Opcode: 51 (0x33) for GCN 1.4<br /> 783 Syntax: S_PACK_LH_B32_B16 SDST, SSRC0, SSRC1<br /> 784 Description: Get first 16 bits from SSRC0 and store in first 16 bits in SDST, 785 Get last 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br /> 786 Operation:<br /> 787 <code>SDST = (SSRC0&0xffff) | (SSRC1&0xffff0000)</code></p> 788 <h4>S_PACK_LL_B32_B16</h4> 789 <p>Opcode: 50 (0x32) for GCN 1.4<br /> 790 Syntax: S_PACK_LL_B32_B16 SDST, SSRC0, SSRC1<br /> 791 Description: Get first 16 bits from SSRC0 and store in first 16 bits in SDST, 792 Get first 16 bits from SSRC1 and store in last 16 bits in SDST. Do not change SCC.<br /> 793 Operation:<br /> 794 <code>SDST = (SSRC0&0xffff) | ((SSRC1&0xffff)<<16)</code></p> 626 795 <h4>S_RFE_RESTORE_B64</h4> 627 <p>Opcode: 43 (0x2b) for GCN 1.2 <br />796 <p>Opcode: 43 (0x2b) for GCN 1.2/1.4<br /> 628 797 Syntax: S_RFE_RESTORE_B64 SDST(2), SSRC0(1)<br /> 629 798 Description: Return from exception handler and set: INST_ATC = SSRC1.U32[0] ???</p> … … 657 826 SCC = (temp>>32)!=0</code></p> 658 827 <h4>S_XNOR_B32</h4> 659 <p>Opcode: 28 (0x1c) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2 <br />828 <p>Opcode: 28 (0x1c) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2/1.4<br /> 660 829 Syntax: S_XNOR_B32 SDST, SSRC0, SSRC1<br /> 661 830 Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 665 834 SCC = SDST!=0</code></p> 666 835 <h4>S_XNOR_B64</h4> 667 <p>Opcode: 29 (0x1d) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2 <br />836 <p>Opcode: 29 (0x1d) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2/1.4<br /> 668 837 Syntax: S_XNOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 669 838 Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 673 842 SCC = SDST!=0</code></p> 674 843 <h4>S_XOR_B32</h4> 675 <p>Opcode: 18 (0x12) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2 <br />844 <p>Opcode: 18 (0x12) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2/1.4<br /> 676 845 Syntax: S_XOR_B32 SDST, SSRC0, SSRC1<br /> 677 846 Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store … … 681 850 SCC = SDST!=0</code></p> 682 851 <h4>S_XOR_B64</h4> 683 <p>Opcode: 19 (0x13) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2 <br />852 <p>Opcode: 19 (0x13) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2/1.4<br /> 684 853 Syntax: S_XOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br /> 685 854 Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store