Changes between Version 8 and Version 9 of GcnInstrsSopk


Ignore:
Timestamp:
11/23/17 21:01:18 (5 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
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  • GcnInstrsSopk

    v8 v9  
    4646<th>Mnemonic (GCN1.0/1.1)</th>
    4747<th>Mnemonic (GCN 1.2)</th>
     48<th>Mnemonic (GCN 1.4)</th>
    4849</tr>
    4950</thead>
     
    5354<td>S_MOVK_I32</td>
    5455<td>S_MOVK_I32</td>
     56<td>S_MOVK_I32</td>
    5557</tr>
    5658<tr>
     
    5860<td>--</td>
    5961<td>S_CMOVK_I32</td>
     62<td>S_CMOVK_I32</td>
    6063</tr>
    6164<tr>
     
    6366<td>S_CMOVK_I32</td>
    6467<td>S_CMPK_EQ_I32</td>
     68<td>S_CMPK_EQ_I32</td>
    6569</tr>
    6670<tr>
     
    6872<td>S_CMPK_EQ_I32</td>
    6973<td>S_CMPK_LG_I32</td>
     74<td>S_CMPK_LG_I32</td>
    7075</tr>
    7176<tr>
     
    7378<td>S_CMPK_LG_I32</td>
    7479<td>S_CMPK_GT_I32</td>
     80<td>S_CMPK_GT_I32</td>
    7581</tr>
    7682<tr>
     
    7884<td>S_CMPK_GT_I32</td>
    7985<td>S_CMPK_GE_I32</td>
     86<td>S_CMPK_GE_I32</td>
    8087</tr>
    8188<tr>
     
    8390<td>S_CMPK_GE_I32</td>
    8491<td>S_CMPK_LT_I32</td>
     92<td>S_CMPK_LT_I32</td>
    8593</tr>
    8694<tr>
     
    8896<td>S_CMPK_LT_I32</td>
    8997<td>S_CMPK_LE_I32</td>
     98<td>S_CMPK_LE_I32</td>
    9099</tr>
    91100<tr>
     
    93102<td>S_CMPK_LE_I32</td>
    94103<td>S_CMPK_EQ_U32</td>
     104<td>S_CMPK_EQ_U32</td>
    95105</tr>
    96106<tr>
     
    98108<td>S_CMPK_EQ_U32</td>
    99109<td>S_CMPK_LG_U32</td>
     110<td>S_CMPK_LG_U32</td>
    100111</tr>
    101112<tr>
     
    103114<td>S_CMPK_LG_U32</td>
    104115<td>S_CMPK_GT_U32</td>
     116<td>S_CMPK_GT_U32</td>
    105117</tr>
    106118<tr>
     
    108120<td>S_CMPK_GT_U32</td>
    109121<td>S_CMPK_GE_U32</td>
     122<td>S_CMPK_GE_U32</td>
    110123</tr>
    111124<tr>
     
    113126<td>S_CMPK_GE_U32</td>
    114127<td>S_CMPK_LT_U32</td>
     128<td>S_CMPK_LT_U32</td>
    115129</tr>
    116130<tr>
     
    118132<td>S_CMPK_LT_U32</td>
    119133<td>S_CMPK_LE_U32</td>
     134<td>S_CMPK_LE_U32</td>
    120135</tr>
    121136<tr>
     
    123138<td>S_CMPK_LE_U32</td>
    124139<td>S_ADDK_I32</td>
     140<td>S_ADDK_I32</td>
    125141</tr>
    126142<tr>
     
    128144<td>S_ADDK_I32</td>
    129145<td>S_MULK_I32</td>
     146<td>S_MULK_I32</td>
    130147</tr>
    131148<tr>
     
    133150<td>S_MULK_I32</td>
    134151<td>S_CBRANCH_I_FORK</td>
     152<td>S_CBRANCH_I_FORK</td>
    135153</tr>
    136154<tr>
     
    138156<td>S_CBRANCH_I_FORK</td>
    139157<td>S_GETREG_B32</td>
     158<td>S_GETREG_B32</td>
    140159</tr>
    141160<tr>
     
    143162<td>S_GETREG_B32</td>
    144163<td>S_SETREG_B32</td>
     164<td>S_SETREG_B32</td>
    145165</tr>
    146166<tr>
     
    148168<td>S_SETREG_B32</td>
    149169<td>S_GETREG_REGRD_B32</td>
     170<td>S_GETREG_REGRD_B32</td>
    150171</tr>
    151172<tr>
     
    153174<td>S_GETREG_REGRD_B32</td>
    154175<td>S_SETREG_IMM32_B32</td>
     176<td>S_SETREG_IMM32_B32</td>
    155177</tr>
    156178<tr>
     
    158180<td>S_SETREG_IMM32_B32</td>
    159181<td>--</td>
     182<td>S_CALL_B64</td>
    160183</tr>
    161184</tbody>
     
    164187<p>Alphabetically sorted instruction list:</p>
    165188<h4>S_ADDK_I32</h4>
    166 <p>Opcode: 15 (0xf) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
     189<p>Opcode: 15 (0xf) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2/1.4<br />
    167190Syntax: S_ADDK_I32 SDST, SIMM16<br />
    168191Description: Add signed SDST to SIMM16 and store result into SDST and
     
    172195INT64 temp = SEXT64(SDST) + SEXT64(SIMM16)
    173196SCC = temp &gt; ((1LL&lt;&lt;31)-1) || temp &lt; (-1LL&lt;&lt;31)</code></p>
     197<h4>S_CALL_B64</h4>
     198<p>Opcode: 21 (0x15) for GCN 1.4<br />
     199Syntax: S_CALL_B64 SDST(2), RELADDR<br />
     200Description: Call (short) a subroutine. Store address of next instruction to SDST and
     201go to RELADDR (store RELADDR into PC).<br />
     202Operation:<br />
     203<code>SDST = PC + 4
     204PC = RELADDR</code></p>
    174205<h4>S_CBRANCH_I_FORK</h4>
    175 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
     206<p>Opcode: 17 (0x11) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2/1.4<br />
    176207Syntax: S_CBRANCH_I_FORK SSRC0(2), RELADDR<br />
    177208Description: Fork control flow to passed and failed condition, jump to address RELADDR for
     
    203234}</code></p>
    204235<h4>S_CMOVK_I32</h4>
    205 <p>Opcode: 2 (0x2) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2<br />
     236<p>Opcode: 2 (0x2) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2/1.4<br />
    206237Syntax: S_MOVK_I32 SDST, SIMM16<br />
    207238Description: If SCC is 1 then move signed extended 16-bit immediate into SDST.
     
    210241<code>SDST = SCC ? SIMM16 : SDST</code></p>
    211242<h4>S_CMPK_EQ_I32</h4>
    212 <p>Opcode: 3 (0x3) for GCN1.0/1.1; 2 (0x2) for GCN 1.2<br />
     243<p>Opcode: 3 (0x3) for GCN1.0/1.1; 2 (0x2) for GCN 1.2/1.4<br />
    213244Syntax: S_CMPK_EQ_I32 SDST, SIMM16<br />
    214245Description: Compare signed value from SDST with SIMM16. If SDST equal, store 1 to SCC,
     
    217248<code>SCC = (INT32)SDST == SIMM16</code></p>
    218249<h4>S_CMPK_EQ_U32</h4>
    219 <p>Opcode: 9 (0x9) for GCN1.0/1.1; 8 (0x8) for GCN 1.2<br />
     250<p>Opcode: 9 (0x9) for GCN1.0/1.1; 8 (0x8) for GCN 1.2/1.4<br />
    220251Syntax: S_CMPK_EQ_U32 SDST, IMM16<br />
    221252Description: Compare unsigned value from SDST with IMM16. If SDST equal, store 1 to SCC,
     
    224255<code>SCC = SDST == IMM16</code></p>
    225256<h4>S_CMPK_GE_I32</h4>
    226 <p>Opcode: 6 (0x6) for GCN1.0/1.1; 5 (0x5) for GCN 1.2<br />
     257<p>Opcode: 6 (0x6) for GCN1.0/1.1; 5 (0x5) for GCN 1.2/1.4<br />
    227258Syntax: S_CMPK_GE_I32 SDST, SIMM16<br />
    228259Description: Compare signed value from SDST with SIMM16. If SDST greater or equal,
     
    231262<code>SCC = (INT32)SDST &gt;= SIMM16</code></p>
    232263<h4>S_CMPK_GE_U32</h4>
    233 <p>Opcode: 12 (0xc) for GCN1.0/1.1; 11 (0xb) for GCN 1.2<br />
     264<p>Opcode: 12 (0xc) for GCN1.0/1.1; 11 (0xb) for GCN 1.2/1.4<br />
    234265Syntax: S_CMPK_GE_U32 SDST, IMM16<br />
    235266Description: Compare unsigned value from SDST with IMM16. If SDST greater or equal,
     
    238269<code>SCC = SDST &gt;= IMM16</code></p>
    239270<h4>S_CMPK_GT_I32</h4>
    240 <p>Opcode: 5 (0x5) for GCN1.0/1.1; 4 (0x4) for GCN 1.2<br />
     271<p>Opcode: 5 (0x5) for GCN1.0/1.1; 4 (0x4) for GCN 1.2/1.4<br />
    241272Syntax: S_CMPK_GT_I32 SDST, SIMM16<br />
    242273Description: Compare signed value from SDST with SIMM16. If SDST greater, store 1 to SCC,
     
    245276<code>SCC = (INT32)SDST &gt; SIMM16</code></p>
    246277<h4>S_CMPK_GT_U32</h4>
    247 <p>Opcode: 11 (0xb) for GCN1.0/1.1; 10 (0xa) for GCN 1.2<br />
     278<p>Opcode: 11 (0xb) for GCN1.0/1.1; 10 (0xa) for GCN 1.2/1.4<br />
    248279Syntax: S_CMPK_GT_U32 SDST, IMM16<br />
    249280Description: Compare unsigned value from SDST with IMM16. If SDST greater, store 1 to SCC,
     
    252283<code>SCC = SDST &gt; IMM16</code></p>
    253284<h4>S_CMPK_LE_I32</h4>
    254 <p>Opcode: 8 (0x8) for GCN1.0/1.1; 7 (0x7) for GCN 1.2<br />
     285<p>Opcode: 8 (0x8) for GCN1.0/1.1; 7 (0x7) for GCN 1.2/1.4<br />
    255286Syntax: S_CMPK_LE_I32 SDST, SIMM16<br />
    256287Description: Compare signed value from SDST with SIMM16. If SDST less or equal,
     
    259290<code>SCC = (INT32)SDST &lt;= SIMM16</code></p>
    260291<h4>S_CMPK_LE_U32</h4>
    261 <p>Opcode: 14 (0xe) for GCN1.0/1.1; 13 (0xd) for GCN 1.2<br />
     292<p>Opcode: 14 (0xe) for GCN1.0/1.1; 13 (0xd) for GCN 1.2/1.4<br />
    262293Syntax: S_CMPK_LE_U32 SDST, IMM16<br />
    263294Description: Compare unsigned value from SDST with IMM16. If SDST less or equal,
     
    266297<code>SCC = SDST &lt;= IMM16</code></p>
    267298<h4>S_CMPK_LG_I32</h4>
    268 <p>Opcode: 4 (0x4) for GCN1.0/1.1; 3 (0x3) for GCN 1.2<br />
     299<p>Opcode: 4 (0x4) for GCN1.0/1.1; 3 (0x3) for GCN 1.2/1.4<br />
    269300Syntax: S_CMPK_LG_I32 SDST, SIMM16<br />
    270301Description: Compare signed value from SDST with SIMM16. If SDST not equal, store 1 to SCC,
     
    273304<code>SCC = (INT32)SDST != SIMM16</code></p>
    274305<h4>S_CMPK_LG_U32</h4>
    275 <p>Opcode: 10 (0xa) for GCN1.0/1.1; 9 (0x9) for GCN 1.2<br />
     306<p>Opcode: 10 (0xa) for GCN1.0/1.1; 9 (0x9) for GCN 1.2/1.4<br />
    276307Syntax: S_CMPK_LG_U32 SDST, IMM16<br />
    277308Description: Compare unsigned value from SDST with IMM16. If SDST not equal, store 1 to SCC,
     
    280311<code>SCC = SDST != IMM16</code></p>
    281312<h4>S_CMPK_LT_I32</h4>
    282 <p>Opcode: 7 (0x7) for GCN1.0/1.1; 6 (0x6) for GCN 1.2<br />
     313<p>Opcode: 7 (0x7) for GCN1.0/1.1; 6 (0x6) for GCN 1.2/1.4<br />
    283314Syntax: S_CMPK_LT_I32 SDST, SIMM16<br />
    284315Description: Compare signed value from SDST with SIMM16. If SDST less, store 1 to SCC,
     
    287318<code>SCC = (INT32)SDST &lt; SIMM16</code></p>
    288319<h4>S_CMPK_LT_U32</h4>
    289 <p>Opcode: 13 (0xd) for GCN1.0/1.1; 12 (0xc) for GCN 1.2<br />
     320<p>Opcode: 13 (0xd) for GCN1.0/1.1; 12 (0xc) for GCN 1.2/1.4<br />
    290321Syntax: S_CMPK_LT_U32 SDST, IMM16<br />
    291322Description: Compare unsigned value from SDST with IMM16. If SDST less, store 1 to SCC,
     
    294325<code>SCC = SDST &lt; IMM16</code></p>
    295326<h4>S_GETREG_B32</h4>
    296 <p>Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2<br />
     327<p>Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2/1.4<br />
    297328Syntax: S_GETREG_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE)<br />
    298329Description: Store hardware register part to SDST. BITOFFSET (0-31) is first bit in
     
    301332<code>SDST = (HWREG &gt;&gt; BITOFFSET) &amp; ((1U &lt;&lt; BITSIZE) - 1U)</code></p>
    302333<h4>S_GETREG_REGRD_B32</h4>
    303 <p>Opcode: 20 (0x14) for GCN1.0/1.1; 19 (0x13) for GCN 1.2<br />
     334<p>Opcode: 20 (0x14) for GCN1.0/1.1; 19 (0x13) for GCN 1.2/1.4<br />
    304335Syntax: S_GETREG_REGRD_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE)<br />
    305336Description: ???<br />
     
    312343<code>SCC = SIMM16</code></p>
    313344<h4>S_MULK_I32</h4>
    314 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
     345<p>Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2/1.4<br />
    315346Syntax: S_MULK_I32 SDST, SIMM16<br />
    316347Description: Multiply signed SDST with SIMM16 and store result into SDST.
     
    319350<code>SDST = SDST * SIMM16</code></p>
    320351<h4>S_SETREG_B32</h4>
    321 <p>Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2<br />
     352<p>Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2/1.4<br />
    322353Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), SDST<br />
    323354Description: Store value from SDST to part of the hardware register.
     
    328359HWREG = (HWREG &amp; ~mask) | ((SDST&lt;&lt;BITOFFSET) &amp; mask)</code></p>
    329360<h4>S_SETREG_IMM32_B32</h4>
    330 <p>Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2<br />
     361<p>Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2/1.4<br />
    331362Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), IMM32<br />
    332363Description: Store value from IMM32 to part of the hardware register.