Changes between Version 8 and Version 9 of GcnInstrsSopk
- Timestamp:
- 11/23/17 21:01:18 (6 years ago)
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GcnInstrsSopk
v8 v9 46 46 <th>Mnemonic (GCN1.0/1.1)</th> 47 47 <th>Mnemonic (GCN 1.2)</th> 48 <th>Mnemonic (GCN 1.4)</th> 48 49 </tr> 49 50 </thead> … … 53 54 <td>S_MOVK_I32</td> 54 55 <td>S_MOVK_I32</td> 56 <td>S_MOVK_I32</td> 55 57 </tr> 56 58 <tr> … … 58 60 <td>--</td> 59 61 <td>S_CMOVK_I32</td> 62 <td>S_CMOVK_I32</td> 60 63 </tr> 61 64 <tr> … … 63 66 <td>S_CMOVK_I32</td> 64 67 <td>S_CMPK_EQ_I32</td> 68 <td>S_CMPK_EQ_I32</td> 65 69 </tr> 66 70 <tr> … … 68 72 <td>S_CMPK_EQ_I32</td> 69 73 <td>S_CMPK_LG_I32</td> 74 <td>S_CMPK_LG_I32</td> 70 75 </tr> 71 76 <tr> … … 73 78 <td>S_CMPK_LG_I32</td> 74 79 <td>S_CMPK_GT_I32</td> 80 <td>S_CMPK_GT_I32</td> 75 81 </tr> 76 82 <tr> … … 78 84 <td>S_CMPK_GT_I32</td> 79 85 <td>S_CMPK_GE_I32</td> 86 <td>S_CMPK_GE_I32</td> 80 87 </tr> 81 88 <tr> … … 83 90 <td>S_CMPK_GE_I32</td> 84 91 <td>S_CMPK_LT_I32</td> 92 <td>S_CMPK_LT_I32</td> 85 93 </tr> 86 94 <tr> … … 88 96 <td>S_CMPK_LT_I32</td> 89 97 <td>S_CMPK_LE_I32</td> 98 <td>S_CMPK_LE_I32</td> 90 99 </tr> 91 100 <tr> … … 93 102 <td>S_CMPK_LE_I32</td> 94 103 <td>S_CMPK_EQ_U32</td> 104 <td>S_CMPK_EQ_U32</td> 95 105 </tr> 96 106 <tr> … … 98 108 <td>S_CMPK_EQ_U32</td> 99 109 <td>S_CMPK_LG_U32</td> 110 <td>S_CMPK_LG_U32</td> 100 111 </tr> 101 112 <tr> … … 103 114 <td>S_CMPK_LG_U32</td> 104 115 <td>S_CMPK_GT_U32</td> 116 <td>S_CMPK_GT_U32</td> 105 117 </tr> 106 118 <tr> … … 108 120 <td>S_CMPK_GT_U32</td> 109 121 <td>S_CMPK_GE_U32</td> 122 <td>S_CMPK_GE_U32</td> 110 123 </tr> 111 124 <tr> … … 113 126 <td>S_CMPK_GE_U32</td> 114 127 <td>S_CMPK_LT_U32</td> 128 <td>S_CMPK_LT_U32</td> 115 129 </tr> 116 130 <tr> … … 118 132 <td>S_CMPK_LT_U32</td> 119 133 <td>S_CMPK_LE_U32</td> 134 <td>S_CMPK_LE_U32</td> 120 135 </tr> 121 136 <tr> … … 123 138 <td>S_CMPK_LE_U32</td> 124 139 <td>S_ADDK_I32</td> 140 <td>S_ADDK_I32</td> 125 141 </tr> 126 142 <tr> … … 128 144 <td>S_ADDK_I32</td> 129 145 <td>S_MULK_I32</td> 146 <td>S_MULK_I32</td> 130 147 </tr> 131 148 <tr> … … 133 150 <td>S_MULK_I32</td> 134 151 <td>S_CBRANCH_I_FORK</td> 152 <td>S_CBRANCH_I_FORK</td> 135 153 </tr> 136 154 <tr> … … 138 156 <td>S_CBRANCH_I_FORK</td> 139 157 <td>S_GETREG_B32</td> 158 <td>S_GETREG_B32</td> 140 159 </tr> 141 160 <tr> … … 143 162 <td>S_GETREG_B32</td> 144 163 <td>S_SETREG_B32</td> 164 <td>S_SETREG_B32</td> 145 165 </tr> 146 166 <tr> … … 148 168 <td>S_SETREG_B32</td> 149 169 <td>S_GETREG_REGRD_B32</td> 170 <td>S_GETREG_REGRD_B32</td> 150 171 </tr> 151 172 <tr> … … 153 174 <td>S_GETREG_REGRD_B32</td> 154 175 <td>S_SETREG_IMM32_B32</td> 176 <td>S_SETREG_IMM32_B32</td> 155 177 </tr> 156 178 <tr> … … 158 180 <td>S_SETREG_IMM32_B32</td> 159 181 <td>--</td> 182 <td>S_CALL_B64</td> 160 183 </tr> 161 184 </tbody> … … 164 187 <p>Alphabetically sorted instruction list:</p> 165 188 <h4>S_ADDK_I32</h4> 166 <p>Opcode: 15 (0xf) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2 <br />189 <p>Opcode: 15 (0xf) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2/1.4<br /> 167 190 Syntax: S_ADDK_I32 SDST, SIMM16<br /> 168 191 Description: Add signed SDST to SIMM16 and store result into SDST and … … 172 195 INT64 temp = SEXT64(SDST) + SEXT64(SIMM16) 173 196 SCC = temp > ((1LL<<31)-1) || temp < (-1LL<<31)</code></p> 197 <h4>S_CALL_B64</h4> 198 <p>Opcode: 21 (0x15) for GCN 1.4<br /> 199 Syntax: S_CALL_B64 SDST(2), RELADDR<br /> 200 Description: Call (short) a subroutine. Store address of next instruction to SDST and 201 go to RELADDR (store RELADDR into PC).<br /> 202 Operation:<br /> 203 <code>SDST = PC + 4 204 PC = RELADDR</code></p> 174 205 <h4>S_CBRANCH_I_FORK</h4> 175 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2 <br />206 <p>Opcode: 17 (0x11) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2/1.4<br /> 176 207 Syntax: S_CBRANCH_I_FORK SSRC0(2), RELADDR<br /> 177 208 Description: Fork control flow to passed and failed condition, jump to address RELADDR for … … 203 234 }</code></p> 204 235 <h4>S_CMOVK_I32</h4> 205 <p>Opcode: 2 (0x2) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2 <br />236 <p>Opcode: 2 (0x2) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2/1.4<br /> 206 237 Syntax: S_MOVK_I32 SDST, SIMM16<br /> 207 238 Description: If SCC is 1 then move signed extended 16-bit immediate into SDST. … … 210 241 <code>SDST = SCC ? SIMM16 : SDST</code></p> 211 242 <h4>S_CMPK_EQ_I32</h4> 212 <p>Opcode: 3 (0x3) for GCN1.0/1.1; 2 (0x2) for GCN 1.2 <br />243 <p>Opcode: 3 (0x3) for GCN1.0/1.1; 2 (0x2) for GCN 1.2/1.4<br /> 213 244 Syntax: S_CMPK_EQ_I32 SDST, SIMM16<br /> 214 245 Description: Compare signed value from SDST with SIMM16. If SDST equal, store 1 to SCC, … … 217 248 <code>SCC = (INT32)SDST == SIMM16</code></p> 218 249 <h4>S_CMPK_EQ_U32</h4> 219 <p>Opcode: 9 (0x9) for GCN1.0/1.1; 8 (0x8) for GCN 1.2 <br />250 <p>Opcode: 9 (0x9) for GCN1.0/1.1; 8 (0x8) for GCN 1.2/1.4<br /> 220 251 Syntax: S_CMPK_EQ_U32 SDST, IMM16<br /> 221 252 Description: Compare unsigned value from SDST with IMM16. If SDST equal, store 1 to SCC, … … 224 255 <code>SCC = SDST == IMM16</code></p> 225 256 <h4>S_CMPK_GE_I32</h4> 226 <p>Opcode: 6 (0x6) for GCN1.0/1.1; 5 (0x5) for GCN 1.2 <br />257 <p>Opcode: 6 (0x6) for GCN1.0/1.1; 5 (0x5) for GCN 1.2/1.4<br /> 227 258 Syntax: S_CMPK_GE_I32 SDST, SIMM16<br /> 228 259 Description: Compare signed value from SDST with SIMM16. If SDST greater or equal, … … 231 262 <code>SCC = (INT32)SDST >= SIMM16</code></p> 232 263 <h4>S_CMPK_GE_U32</h4> 233 <p>Opcode: 12 (0xc) for GCN1.0/1.1; 11 (0xb) for GCN 1.2 <br />264 <p>Opcode: 12 (0xc) for GCN1.0/1.1; 11 (0xb) for GCN 1.2/1.4<br /> 234 265 Syntax: S_CMPK_GE_U32 SDST, IMM16<br /> 235 266 Description: Compare unsigned value from SDST with IMM16. If SDST greater or equal, … … 238 269 <code>SCC = SDST >= IMM16</code></p> 239 270 <h4>S_CMPK_GT_I32</h4> 240 <p>Opcode: 5 (0x5) for GCN1.0/1.1; 4 (0x4) for GCN 1.2 <br />271 <p>Opcode: 5 (0x5) for GCN1.0/1.1; 4 (0x4) for GCN 1.2/1.4<br /> 241 272 Syntax: S_CMPK_GT_I32 SDST, SIMM16<br /> 242 273 Description: Compare signed value from SDST with SIMM16. If SDST greater, store 1 to SCC, … … 245 276 <code>SCC = (INT32)SDST > SIMM16</code></p> 246 277 <h4>S_CMPK_GT_U32</h4> 247 <p>Opcode: 11 (0xb) for GCN1.0/1.1; 10 (0xa) for GCN 1.2 <br />278 <p>Opcode: 11 (0xb) for GCN1.0/1.1; 10 (0xa) for GCN 1.2/1.4<br /> 248 279 Syntax: S_CMPK_GT_U32 SDST, IMM16<br /> 249 280 Description: Compare unsigned value from SDST with IMM16. If SDST greater, store 1 to SCC, … … 252 283 <code>SCC = SDST > IMM16</code></p> 253 284 <h4>S_CMPK_LE_I32</h4> 254 <p>Opcode: 8 (0x8) for GCN1.0/1.1; 7 (0x7) for GCN 1.2 <br />285 <p>Opcode: 8 (0x8) for GCN1.0/1.1; 7 (0x7) for GCN 1.2/1.4<br /> 255 286 Syntax: S_CMPK_LE_I32 SDST, SIMM16<br /> 256 287 Description: Compare signed value from SDST with SIMM16. If SDST less or equal, … … 259 290 <code>SCC = (INT32)SDST <= SIMM16</code></p> 260 291 <h4>S_CMPK_LE_U32</h4> 261 <p>Opcode: 14 (0xe) for GCN1.0/1.1; 13 (0xd) for GCN 1.2 <br />292 <p>Opcode: 14 (0xe) for GCN1.0/1.1; 13 (0xd) for GCN 1.2/1.4<br /> 262 293 Syntax: S_CMPK_LE_U32 SDST, IMM16<br /> 263 294 Description: Compare unsigned value from SDST with IMM16. If SDST less or equal, … … 266 297 <code>SCC = SDST <= IMM16</code></p> 267 298 <h4>S_CMPK_LG_I32</h4> 268 <p>Opcode: 4 (0x4) for GCN1.0/1.1; 3 (0x3) for GCN 1.2 <br />299 <p>Opcode: 4 (0x4) for GCN1.0/1.1; 3 (0x3) for GCN 1.2/1.4<br /> 269 300 Syntax: S_CMPK_LG_I32 SDST, SIMM16<br /> 270 301 Description: Compare signed value from SDST with SIMM16. If SDST not equal, store 1 to SCC, … … 273 304 <code>SCC = (INT32)SDST != SIMM16</code></p> 274 305 <h4>S_CMPK_LG_U32</h4> 275 <p>Opcode: 10 (0xa) for GCN1.0/1.1; 9 (0x9) for GCN 1.2 <br />306 <p>Opcode: 10 (0xa) for GCN1.0/1.1; 9 (0x9) for GCN 1.2/1.4<br /> 276 307 Syntax: S_CMPK_LG_U32 SDST, IMM16<br /> 277 308 Description: Compare unsigned value from SDST with IMM16. If SDST not equal, store 1 to SCC, … … 280 311 <code>SCC = SDST != IMM16</code></p> 281 312 <h4>S_CMPK_LT_I32</h4> 282 <p>Opcode: 7 (0x7) for GCN1.0/1.1; 6 (0x6) for GCN 1.2 <br />313 <p>Opcode: 7 (0x7) for GCN1.0/1.1; 6 (0x6) for GCN 1.2/1.4<br /> 283 314 Syntax: S_CMPK_LT_I32 SDST, SIMM16<br /> 284 315 Description: Compare signed value from SDST with SIMM16. If SDST less, store 1 to SCC, … … 287 318 <code>SCC = (INT32)SDST < SIMM16</code></p> 288 319 <h4>S_CMPK_LT_U32</h4> 289 <p>Opcode: 13 (0xd) for GCN1.0/1.1; 12 (0xc) for GCN 1.2 <br />320 <p>Opcode: 13 (0xd) for GCN1.0/1.1; 12 (0xc) for GCN 1.2/1.4<br /> 290 321 Syntax: S_CMPK_LT_U32 SDST, IMM16<br /> 291 322 Description: Compare unsigned value from SDST with IMM16. If SDST less, store 1 to SCC, … … 294 325 <code>SCC = SDST < IMM16</code></p> 295 326 <h4>S_GETREG_B32</h4> 296 <p>Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2 <br />327 <p>Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2/1.4<br /> 297 328 Syntax: S_GETREG_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE)<br /> 298 329 Description: Store hardware register part to SDST. BITOFFSET (0-31) is first bit in … … 301 332 <code>SDST = (HWREG >> BITOFFSET) & ((1U << BITSIZE) - 1U)</code></p> 302 333 <h4>S_GETREG_REGRD_B32</h4> 303 <p>Opcode: 20 (0x14) for GCN1.0/1.1; 19 (0x13) for GCN 1.2 <br />334 <p>Opcode: 20 (0x14) for GCN1.0/1.1; 19 (0x13) for GCN 1.2/1.4<br /> 304 335 Syntax: S_GETREG_REGRD_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE)<br /> 305 336 Description: ???<br /> … … 312 343 <code>SCC = SIMM16</code></p> 313 344 <h4>S_MULK_I32</h4> 314 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2 <br />345 <p>Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2/1.4<br /> 315 346 Syntax: S_MULK_I32 SDST, SIMM16<br /> 316 347 Description: Multiply signed SDST with SIMM16 and store result into SDST. … … 319 350 <code>SDST = SDST * SIMM16</code></p> 320 351 <h4>S_SETREG_B32</h4> 321 <p>Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2 <br />352 <p>Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2/1.4<br /> 322 353 Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), SDST<br /> 323 354 Description: Store value from SDST to part of the hardware register. … … 328 359 HWREG = (HWREG & ~mask) | ((SDST<<BITOFFSET) & mask)</code></p> 329 360 <h4>S_SETREG_IMM32_B32</h4> 330 <p>Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2 <br />361 <p>Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2/1.4<br /> 331 362 Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), IMM32<br /> 332 363 Description: Store value from IMM32 to part of the hardware register.