Changes between Version 29 and Version 30 of GcnInstrsVop1

Timestamp:

06/17/17 11:00:27 (7 years ago)

Author:

trac

Comment:

--

GcnInstrsVop1

@@ -1453 +1453 @@
 else
     VDST = NAN * SIGN(SD)</code></p>
+<h4>V_FREXP_EXP_I16_F16</h4>
+<p>Opcode VOP1: 67 (0x43) for GCN 1.2<br />
+Opcode VOP3A: 387 (0x183) for GCN 1.2<br />
+Syntax: V_FREXP_EXP_I16_F16 VDST, SRC0<br />
+Description: Get exponent plus 1 from half FP value SRC0, and store that exponent to VDST
+as 16-bit signed integer. This instruction realizes frexp function.
+If SRC0 is infinity or NAN then store 0 to VDST.<br />
+Operation:<br />
+<code>HALF SF = ASHALF(SRC0)
+if (ABS(SF) != INF_H &amp;&amp; !ISNAN(SF))
+    VDST = (INT16)FREXP_EXP(SF)
+else
+    VDST = 0</code></p>
 <h4>V_FREXP_EXP_I32_F32</h4>
 <p>Opcode VOP1: 63 (0x3f) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2<br />
@@ -1459 +1472 @@
 Description: Get exponent plus 1 from single FP value SRC0, and store that exponent to VDST.
 This instruction realizes frexp function.
-If SRC0 is infinity or NAN then store -1 to VDST.<br />
+If SRC0 is infinity or NAN then store -1 if GCN 1.0 or 0 to VDST.<br />
 Operation:<br />
 <code>FLOAT SF = ASFLOAT(SRC0)
@@ -1465 +1478 @@
     VDST = FREXP_EXP(SF)
 else
-    VDST = -1</code></p>
+    VDST = -1 // GCN 1.0
+    VDST = 0 // later</code></p>
 <h4>V_FREXP_EXP_I32_F64</h4>
 <p>Opcode VOP1: 60 (0x3c) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2<br />
@@ -1472 +1486 @@
 Description: Get exponent plus 1 from double FP value SRC0, and store that exponent to VDST.
 This instruction realizes frexp function.
-If SRC0 is infinity or NAN then store -1 to VDST.<br />
+If SRC0 is infinity or NAN then store -1 if GCN 1.0 or 0 to VDST.<br />
 Operation:<br />
 <code>DOUBLE SD = ASDOUBLE(SRC0)
@@ -1478 +1492 @@
     VDST = FREXP_EXP(SD)
 else
-    VDST = -1</code></p>
+    VDST = -1 // GCN 1.0
+    VDST = 0 // later</code></p>
+<h4>V_FREXP_MANT_F16</h4>
+<p>Opcode VOP1: 66 (0x42) for GCN 1.2<br />
+Opcode VOP3A: 386 (0x182) for GCN 1.2<br />
+Syntax: V_FREXP_MANT_F16 VDST, SRC0<br />
+Description: Get mantisa from half FP value SRC0, and store it to VDST. Mantisa includes
+sign of input.<br />
+Operation:<br />
+<code>HALF SF = ASHALF(SRC0)
+if (ABS(SF) == INF)
+    VDST = SF
+else if (!ISNAN(SF))
+    VDST = FREXP_MANT(SF) * SIGN(SF)
+else
+    VDST = NAN_H * SIGN(SF)</code></p>
 <h4>V_FREXP_MANT_F32</h4>
 <p>Opcode VOP1: 64 (0x40) for GCN 1.0/1.1; 52 (0x34) for GCN 1.2<br />
 Opcode VOP3A: 448 (0x1c0) for GCN 1.0/1.1; 372 (0x174) for GCN 1.2<br />
 Syntax: V_FREXP_MANT_F32 VDST, SRC0<br />
-Description: Get mantisa from double FP value SRC0, and store it to VDST. Mantisa includes
-sign of input. If SRC0 is infinity then store -NAN to VDST.<br />
+Description: Get mantisa from single FP value SRC0, and store it to VDST. Mantisa includes
+sign of input. For GCN 1.0, if SRC0 is infinity then store -NAN to VDST.<br />
 Operation:<br />
 <code>FLOAT SF = ASFLOAT(SRC0)
 if (ABS(SF) == INF)
-    VDST = -NAN
+    VDST = -NAN // GCN 1.0
+    VDST = SF // later
 else if (!ISNAN(SF))
     VDST = FREXP_MANT(SF) * SIGN(SF)
@@ -1502 +1532 @@
 <code>DOUBLE SD = ASDOUBLE(SRC0)
 if (ABS(SD) == INF)
-    VDST = -NAN
+    VDST = -NAN // GCN 1.0
+    VDST = SF // later
 else if (!ISNAN(SD))
     VDST = FREXP_MANT(SD) * SIGN(SD)