Changes between Version 30 and Version 31 of GcnInstrsVop1
 Timestamp:
 06/17/17 12:00:27 (5 years ago)
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GcnInstrsVop1
v30 v31 1085 1085 Operation:<br /> 1086 1086 <code>VDST = REVBIT(SRC0)</code></p> 1087 <h4>V_CEIL_F16</h4> 1088 <p>Opcode VOP1: 69 (0x45) for GCN 1.2<br /> 1089 Opcode VOP3A: 389 (0x185) for GCN 1.2<br /> 1090 Syntax: V_CEIL_F16 VDST, SRC0<br /> 1091 Description: Truncate half floating point valu from SRC0 with rounding to positive infinity 1092 (ceilling), and store result to VDST. Implemented by flooring. 1093 If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1094 Operation:<br /> 1095 <code>HALF F = FLOOR(ASHALF(SRC0)) 1096 if (ASHALF(SRC0) > 0.0 && ASHALF(SRC0) != F) 1097 F += 1.0 1098 VDST = F</code></p> 1087 1099 <h4>V_CEIL_F32</h4> 1088 1100 <p>Opcode VOP1: 34 (0x22) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br /> … … 1114 1126 Syntax: V_CLREXCP<br /> 1115 1127 Description: Clear wave's exception state in SIMD. </p> 1128 <h4>V_COS_F16</h4> 1129 <p>Opcode VOP1: 74 (0x4a) for GCN 1.2<br /> 1130 Opcode VOP3A: 394 (0x18a) for GCN 1.2<br /> 1131 Syntax: V_COS_F16 VDST, SRC0<br /> 1132 Description: Compute cosine of half FP value from SRC0. 1133 Input value must be normalized to range 1.0  1.0 (360 degree : 360 degree). 1134 If SRC0 value is out of range then store 1.0 to VDST. 1135 If SRC0 value is infinity, store NAN to VDST.<br /> 1136 Operation:<br /> 1137 <code>FLOAT SF = ASHALF(SRC0) 1138 VDST = 1.0 1139 if (SF >= 1.0 && SF <= 1.0) 1140 VDST = APPROX_COS(SF) 1141 else if (ABS(SF)==INF_H) 1142 VDST = NAN_H 1143 else if (ISNAN(SF)) 1144 VDST = SRC0</code></p> 1116 1145 <h4>V_COS_F32</h4> 1117 1146 <p>Opcode VOP1: 54 (0x36) for GCN 1.0/1.1; 42 (0x2a) for GCN 1.2<br /> … … 1411 1440 if ((1U<<i) & SRC0) != 0) 1412 1441 { VDST = i; break; }</code></p> 1442 <h4>V_FLOOR_F16</h4> 1443 <p>Opcode VOP1: 68 (0x44) for GCN 1.2<br /> 1444 Opcode VOP3A: 388 (0x184) for GCN 1.2<br /> 1445 Syntax: V_FLOOR_F16 VDST, SRC0<br /> 1446 Description: Truncate half floating point value SRC0 with rounding to negative infinity 1447 (flooring), and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1448 Operation:<br /> 1449 <code>VDST = FLOOR(ASHALF(SRC0))</code></p> 1413 1450 <h4>V_FLOOR_F32</h4> 1414 1451 <p>Opcode VOP1: 36 (0x24) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br /> 1415 1452 Opcode VOP3A: 420 (0x1a4) for GCN 1.0/1.1; 351 (0x15f) for GCN 1.2<br /> 1416 1453 Syntax: V_FLOOR_F32 VDST, SRC0<br /> 1417 Description: Truncate floating point value SRC0 with rounding to positive infinity1454 Description: Truncate floating point value SRC0 with rounding to negative infinity 1418 1455 (flooring), and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1419 1456 Operation:<br /> … … 1423 1460 Opcode VOP3A: 410 (0x19a) for GCN 1.1; 346 (0x15a) for GCN 1.2<br /> 1424 1461 Syntax: V_FLOOR_F64 VDST(2), SRC0(2)<br /> 1425 Description: Truncate double floating point value SRC0 with rounding to positive infinity1462 Description: Truncate double floating point value SRC0 with rounding to negative infinity 1426 1463 (flooring), and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1427 1464 Operation:<br /> … … 1733 1770 { firstlane = i; break; } 1734 1771 SDST = VSRC0[firstlane]</code></p> 1772 <h4>V_RNDNE_F16</h4> 1773 <p>Opcode VOP1: 71 (0x47) for GCN 1.2<br /> 1774 Opcode VOP3A: 391 (0x187) for GCN 1.2<br /> 1775 Syntax: V_RNDNE_F16 VDST, SRC0<br /> 1776 Description: Round half floating point value SRC0 to nearest even integer, 1777 and store result to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1778 Operation:<br /> 1779 <code>VDST = RNDNE(ASHALF(SRC0))</code></p> 1735 1780 <h4>V_RNDNE_F32</h4> 1736 1781 <p>Opcode VOP1: 35 (0x23) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br /> … … 1810 1855 if (ASFLOAT(VDST)==INF) 1811 1856 VDST = 0.0</code></p> 1857 <h4>V_SIN_F16</h4> 1858 <p>Opcode VOP1: 73 (0x49) for GCN 1.2<br /> 1859 Opcode VOP3A: 393 (0x189) for GCN 1.2<br /> 1860 Syntax: V_SIN_F16 VDST, SRC0<br /> 1861 Description: Compute sine of half FP value from SRC0. Input value must be 1862 normalized to range 1.0  1.0 (360 degree : 360 degree). 1863 If SRC0 value is out of range then store 0.0 to VDST. 1864 If SRC0 value is infinity, store NAN to VDST.<br /> 1865 Operation:<br /> 1866 <code>HALF SF = ASHALF(SRC0) 1867 VDST = 0.0 1868 if (SF >= 1.0 && SF <= 1.0) 1869 VDST = APPROX_SIN(SF) 1870 else if (ABS(SF)==INF_H) 1871 VDST = NAN_H 1872 else if (ISNAN(SF)) 1873 VDST = SRC0</code></p> 1812 1874 <h4>V_SIN_F32</h4> 1813 1875 <p>Opcode VOP1: 53 (0x35) for GCN 1.0/1.1; 41 (0x29) for GCN 1.2<br /> … … 1860 1922 else 1861 1923 VDST = NAN</code></p> 1924 <h4>V_TRUNC_F16</h4> 1925 <p>Opcode VOP1: 70 (0x46) for GCN 1.2<br /> 1926 Opcode VOP3A: 390 (0x186) for GCN 1.2<br /> 1927 Syntax: V_TRUNC_F16 VDST, SRC0<br /> 1928 Description: Get integer value from half floating point value SRC0, and store (as half) 1929 it to VDST. If SRC0 is infinity or NaN then copy SRC0 to VDST.<br /> 1930 Operation:<br /> 1931 <code>VDST = RNDTZ(ASHALF(SRC0))</code></p> 1862 1932 <h4>V_TRUNC_F32</h4> 1863 1933 <p>Opcode VOP1: 33 (0x21) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />