Changes between Version 31 and Version 32 of GcnInstrsVop1

Timestamp:

06/17/17 14:00:30 (7 years ago)

Author:

trac

Comment:

--

GcnInstrsVop1

@@ -1164 +1164 @@
 Syntax: V_CVT_F16_F32 VDST, SRC0<br />
 Description: Convert single FP value to half floating point value with rounding from
-MODE register (single FP rounding mode), and store result to VDST.
-If absolute value is too high, then store -/+infinity to VDST.
+MODE register (single FP rounding mode for GCN 1.0, double FP rounding modefor GCN 1.2),
+and store result to VDST. If absolute value is too high, then store -/+infinity to VDST.
 In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled.<br />
 Operation:<br />
@@ -1379 +1379 @@
 Opcode VOP3A: 385 (0x181) for GCN 1.2<br />
 Syntax: V_EXP_F16 VDST, SRC0<br />
-Description: Approximate power of two from half FP value SRC0 and store it to VDST.
-Instruction always handles dernomals in output regardless floatmode in MODE register.<br />
+Description: Approximate power of two from half FP value SRC0 and store it to VDST.<br />
 Operation:<br />
 <code>VDST = APPROX_POW2(ASHALF(SRC0))</code></p>
@@ -1600 +1599 @@
 Syntax: V_LOG_F16 VDST, SRC0<br />
 Description: Approximate logarithm of base 2 from half floating point value SRC0, and store
-result to VDST. If SRC0 is negative then store -NaN to VDST.
-This instruction handle denormalized values regardless FLOAT MODE register setup.<br />
+result to VDST. If SRC0 is negative then store -NaN to VDST.<br />
 Operation:<br />
 <code>HALF F = ASHALF(SRC0)
@@ -1822 +1820 @@
 Syntax: V_RSQ_F16 VDST, SRC0<br />
 Description: Approximate reciprocal square root from half floating point value SRC0 and
-store it to VDST. If SRC0 is negative value, store -NAN to VDST.
-This instruction doesn't handle denormalized values regardless FLOAT MODE register setup.<br />
+store it to VDST. If SRC0 is negative value, store -NAN to VDST.<br />
 Operation:<br />
 <code>VDST = APPROX_RSQRT(ASHALF(SRC0))</code></p>