Changes between Version 28 and Version 29 of GcnInstrsVop3
- Timestamp:
- 11/25/17 14:00:31 (6 years ago)
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GcnInstrsVop3
v28 v29 463 463 </tbody> 464 464 </table> 465 <p>List of the instructions by opcode (GCN 1.2 ):</p>465 <p>List of the instructions by opcode (GCN 1.2/1.4):</p> 466 466 <table> 467 467 <thead> 468 468 <tr> 469 469 <th>Opcode</th> 470 <th>GCN 1.2</th> 471 <th>GCN 1.4</th> 470 472 <th>Mnemonic</th> 471 473 </tr> … … 474 476 <tr> 475 477 <td>448 (0x1c0)</td> 478 <td>✓</td> 479 <td>✓</td> 476 480 <td>V_MAD_LEGACY_F32</td> 477 481 </tr> 478 482 <tr> 479 483 <td>449 (0x1c1)</td> 484 <td>✓</td> 485 <td>✓</td> 480 486 <td>V_MAD_F32</td> 481 487 </tr> 482 488 <tr> 483 489 <td>450 (0x1c2)</td> 490 <td>✓</td> 491 <td>✓</td> 484 492 <td>V_MAD_I32_I24</td> 485 493 </tr> 486 494 <tr> 487 495 <td>451 (0x1c3)</td> 496 <td>✓</td> 497 <td>✓</td> 488 498 <td>V_MAD_U32_U24</td> 489 499 </tr> 490 500 <tr> 491 501 <td>452 (0x1c4)</td> 502 <td>✓</td> 503 <td>✓</td> 492 504 <td>V_CUBEID_F32</td> 493 505 </tr> 494 506 <tr> 495 507 <td>453 (0x1c5)</td> 508 <td>✓</td> 509 <td>✓</td> 496 510 <td>V_CUBESC_F32</td> 497 511 </tr> 498 512 <tr> 499 513 <td>454 (0x1c6)</td> 514 <td>✓</td> 515 <td>✓</td> 500 516 <td>V_CUBETC_F32</td> 501 517 </tr> 502 518 <tr> 503 519 <td>455 (0x1c7)</td> 520 <td>✓</td> 521 <td>✓</td> 504 522 <td>V_CUBEMA_F32</td> 505 523 </tr> 506 524 <tr> 507 525 <td>456 (0x1c8)</td> 526 <td>✓</td> 527 <td>✓</td> 508 528 <td>V_BFE_U32</td> 509 529 </tr> 510 530 <tr> 511 531 <td>457 (0x1c9)</td> 532 <td>✓</td> 533 <td>✓</td> 512 534 <td>V_BFE_I32</td> 513 535 </tr> 514 536 <tr> 515 537 <td>458 (0x1ca)</td> 538 <td>✓</td> 539 <td>✓</td> 516 540 <td>V_BFI_B32</td> 517 541 </tr> 518 542 <tr> 519 543 <td>459 (0x1cb)</td> 544 <td>✓</td> 545 <td>✓</td> 520 546 <td>V_FMA_F32</td> 521 547 </tr> 522 548 <tr> 523 549 <td>460 (0x1cc)</td> 550 <td>✓</td> 551 <td>✓</td> 524 552 <td>V_FMA_F64</td> 525 553 </tr> 526 554 <tr> 527 555 <td>461 (0x1cd)</td> 556 <td>✓</td> 557 <td>✓</td> 528 558 <td>V_LERP_U8</td> 529 559 </tr> 530 560 <tr> 531 561 <td>462 (0x1ce)</td> 562 <td>✓</td> 563 <td>✓</td> 532 564 <td>V_ALIGNBIT_B32</td> 533 565 </tr> 534 566 <tr> 535 567 <td>463 (0x1cf)</td> 568 <td>✓</td> 569 <td>✓</td> 536 570 <td>V_ALIGNBYTE_B32</td> 537 571 </tr> 538 572 <tr> 539 573 <td>464 (0x1d0)</td> 574 <td>✓</td> 575 <td>✓</td> 540 576 <td>V_MIN3_F32</td> 541 577 </tr> 542 578 <tr> 543 579 <td>465 (0x1d1)</td> 580 <td>✓</td> 581 <td>✓</td> 544 582 <td>V_MIN3_I32</td> 545 583 </tr> 546 584 <tr> 547 585 <td>466 (0x1d2)</td> 586 <td>✓</td> 587 <td>✓</td> 548 588 <td>V_MIN3_U32</td> 549 589 </tr> 550 590 <tr> 551 591 <td>467 (0x1d3)</td> 592 <td>✓</td> 593 <td>✓</td> 552 594 <td>V_MAX3_F32</td> 553 595 </tr> 554 596 <tr> 555 597 <td>468 (0x1d4)</td> 598 <td>✓</td> 599 <td>✓</td> 556 600 <td>V_MAX3_I32</td> 557 601 </tr> 558 602 <tr> 559 603 <td>469 (0x1d5)</td> 604 <td>✓</td> 605 <td>✓</td> 560 606 <td>V_MAX3_U32</td> 561 607 </tr> 562 608 <tr> 563 609 <td>470 (0x1d6)</td> 610 <td>✓</td> 611 <td>✓</td> 564 612 <td>V_MED3_F32</td> 565 613 </tr> 566 614 <tr> 567 615 <td>471 (0x1d7)</td> 616 <td>✓</td> 617 <td>✓</td> 568 618 <td>V_MED3_I32</td> 569 619 </tr> 570 620 <tr> 571 621 <td>472 (0x1d8)</td> 622 <td>✓</td> 623 <td>✓</td> 572 624 <td>V_MED3_U32</td> 573 625 </tr> 574 626 <tr> 575 627 <td>473 (0x1d9)</td> 628 <td>✓</td> 629 <td>✓</td> 576 630 <td>V_SAD_U8</td> 577 631 </tr> 578 632 <tr> 579 633 <td>474 (0x1da)</td> 634 <td>✓</td> 635 <td>✓</td> 580 636 <td>V_SAD_HI_U8</td> 581 637 </tr> 582 638 <tr> 583 639 <td>475 (0x1db)</td> 640 <td>✓</td> 641 <td>✓</td> 584 642 <td>V_SAD_U16</td> 585 643 </tr> 586 644 <tr> 587 645 <td>476 (0x1dc)</td> 646 <td>✓</td> 647 <td>✓</td> 588 648 <td>V_SAD_U32</td> 589 649 </tr> 590 650 <tr> 591 651 <td>477 (0x1dd)</td> 652 <td>✓</td> 653 <td>✓</td> 592 654 <td>V_CVT_PK_U8_F32</td> 593 655 </tr> 594 656 <tr> 595 657 <td>478 (0x1de)</td> 658 <td>✓</td> 659 <td>✓</td> 596 660 <td>V_DIV_FIXUP_F32</td> 597 661 </tr> 598 662 <tr> 599 663 <td>479 (0x1df)</td> 664 <td>✓</td> 665 <td>✓</td> 600 666 <td>V_DIV_FIXUP_F64</td> 601 667 </tr> 602 668 <tr> 603 669 <td>480 (0x1e0)</td> 670 <td>✓</td> 671 <td>✓</td> 604 672 <td>V_DIV_SCALE_F32 (VOP3B)</td> 605 673 </tr> 606 674 <tr> 607 675 <td>481 (0x1e1)</td> 676 <td>✓</td> 677 <td>✓</td> 608 678 <td>V_DIV_SCALE_F64 (VOP3B)</td> 609 679 </tr> 610 680 <tr> 611 681 <td>482 (0x1e2)</td> 682 <td>✓</td> 683 <td>✓</td> 612 684 <td>V_DIV_FMAS_F32</td> 613 685 </tr> 614 686 <tr> 615 687 <td>483 (0x1e3)</td> 688 <td>✓</td> 689 <td>✓</td> 616 690 <td>V_DIV_FMAS_F64</td> 617 691 </tr> 618 692 <tr> 619 693 <td>484 (0x1e4)</td> 694 <td>✓</td> 695 <td>✓</td> 620 696 <td>V_MSAD_U8</td> 621 697 </tr> 622 698 <tr> 623 699 <td>485 (0x1e5)</td> 700 <td>✓</td> 701 <td>✓</td> 624 702 <td>V_QSAD_PK_U16_U8</td> 625 703 </tr> 626 704 <tr> 627 705 <td>486 (0x1e6)</td> 706 <td>✓</td> 707 <td>✓</td> 628 708 <td>V_MQSAD_PK_U16_U8</td> 629 709 </tr> 630 710 <tr> 631 711 <td>487 (0x1e7)</td> 712 <td>✓</td> 713 <td>✓</td> 632 714 <td>V_MQSAD_U32_U8</td> 633 715 </tr> 634 716 <tr> 635 717 <td>488 (0x1e8)</td> 718 <td>✓</td> 719 <td>✓</td> 636 720 <td>V_MAD_U64_U32 (VOP3B)</td> 637 721 </tr> 638 722 <tr> 639 723 <td>489 (0x1e9)</td> 724 <td>✓</td> 725 <td>✓</td> 640 726 <td>V_MAD_I64_I32 (VOP3B)</td> 641 727 </tr> 642 728 <tr> 643 729 <td>490 (0x1ea)</td> 730 <td>✓</td> 731 <td>✓</td> 644 732 <td>V_MAD_F16</td> 645 733 </tr> 646 734 <tr> 647 735 <td>491 (0x1eb)</td> 736 <td>✓</td> 737 <td>✓</td> 648 738 <td>V_MAD_U16</td> 649 739 </tr> 650 740 <tr> 651 741 <td>492 (0x1ec)</td> 742 <td>✓</td> 743 <td>✓</td> 652 744 <td>V_MAD_I16</td> 653 745 </tr> 654 746 <tr> 655 747 <td>493 (0x1ed)</td> 748 <td>✓</td> 749 <td>✓</td> 656 750 <td>V_PERM_B32</td> 657 751 </tr> 658 752 <tr> 659 753 <td>494 (0x1ee)</td> 754 <td>✓</td> 755 <td>✓</td> 660 756 <td>V_FMA_F16</td> 661 757 </tr> 662 758 <tr> 663 759 <td>495 (0x1ef)</td> 760 <td>✓</td> 761 <td>✓</td> 664 762 <td>V_DIV_FIXUP_F16</td> 665 763 </tr> 666 764 <tr> 667 765 <td>496 (0x1f0)</td> 766 <td>✓</td> 767 <td>✓</td> 668 768 <td>V_CVT_PKACCUM_U8_F32</td> 669 769 </tr> 670 770 <tr> 671 771 <td>624 (0x270)</td> 772 <td>✓</td> 773 <td>✓</td> 672 774 <td>V_INTERP_P1_F32 (VINTRP)</td> 673 775 </tr> 674 776 <tr> 675 777 <td>625 (0x271)</td> 778 <td>✓</td> 779 <td>✓</td> 676 780 <td>V_INTERP_P2_F32 (VINTRP)</td> 677 781 </tr> 678 782 <tr> 679 783 <td>626 (0x272)</td> 784 <td>✓</td> 785 <td>✓</td> 680 786 <td>V_INTERP_MOV_F32 (VINTRP)</td> 681 787 </tr> 682 788 <tr> 683 789 <td>627 (0x273)</td> 790 <td>✓</td> 791 <td>✓</td> 684 792 <td>V_INTERP_P1LL_F16 (VINTRP)</td> 685 793 </tr> 686 794 <tr> 687 795 <td>628 (0x274)</td> 796 <td>✓</td> 797 <td>✓</td> 688 798 <td>V_INTERP_P1LV_F16 (VINTRP)</td> 689 799 </tr> 690 800 <tr> 691 801 <td>629 (0x275)</td> 802 <td>✓</td> 803 <td>✓</td> 692 804 <td>V_INTERP_P2_F16 (VINTRP)</td> 693 805 </tr> 694 806 <tr> 695 807 <td>640 (0x280)</td> 808 <td>✓</td> 809 <td>✓</td> 696 810 <td>V_ADD_F64</td> 697 811 </tr> 698 812 <tr> 699 813 <td>641 (0x281)</td> 814 <td>✓</td> 815 <td>✓</td> 700 816 <td>V_MUL_F64</td> 701 817 </tr> 702 818 <tr> 703 819 <td>642 (0x282)</td> 820 <td>✓</td> 821 <td>✓</td> 704 822 <td>V_MIN_F64</td> 705 823 </tr> 706 824 <tr> 707 825 <td>643 (0x283)</td> 826 <td>✓</td> 827 <td>✓</td> 708 828 <td>V_MAX_F64</td> 709 829 </tr> 710 830 <tr> 711 831 <td>644 (0x284)</td> 832 <td>✓</td> 833 <td>✓</td> 712 834 <td>V_LDEXP_F64</td> 713 835 </tr> 714 836 <tr> 715 837 <td>645 (0x285)</td> 838 <td>✓</td> 839 <td>✓</td> 716 840 <td>V_MUL_LO_U32</td> 717 841 </tr> 718 842 <tr> 719 843 <td>646 (0x286)</td> 844 <td>✓</td> 845 <td>✓</td> 720 846 <td>V_MUL_HI_U32</td> 721 847 </tr> 722 848 <tr> 723 849 <td>647 (0x287)</td> 850 <td>✓</td> 851 <td>✓</td> 724 852 <td>V_MUL_HI_I32</td> 725 853 </tr> 726 854 <tr> 727 855 <td>648 (0x288)</td> 856 <td>✓</td> 857 <td>✓</td> 728 858 <td>V_LDEXP_F32</td> 729 859 </tr> 730 860 <tr> 731 861 <td>649 (0x289)</td> 862 <td>✓</td> 863 <td>✓</td> 732 864 <td>V_READLANE_B32</td> 733 865 </tr> 734 866 <tr> 735 867 <td>650 (0x28a)</td> 868 <td>✓</td> 869 <td>✓</td> 736 870 <td>V_WRITELANE_B32</td> 737 871 </tr> 738 872 <tr> 739 873 <td>651 (0x28b)</td> 874 <td>✓</td> 875 <td>✓</td> 740 876 <td>V_BCNT_U32_B32</td> 741 877 </tr> 742 878 <tr> 743 879 <td>652 (0x28c)</td> 880 <td>✓</td> 881 <td>✓</td> 744 882 <td>V_MBCNT_LO_U32_B32</td> 745 883 </tr> 746 884 <tr> 747 885 <td>653 (0x28d)</td> 886 <td>✓</td> 887 <td>✓</td> 748 888 <td>V_MBCNT_HI_U32_B32</td> 749 889 </tr> 750 890 <tr> 751 891 <td>654 (0x28e)</td> 892 <td>✓</td> 893 <td>✓</td> 752 894 <td>V_MAC_LEGACY_F32</td> 753 895 </tr> 754 896 <tr> 755 897 <td>655 (0x28f)</td> 898 <td>✓</td> 899 <td>✓</td> 756 900 <td>V_LSHLREV_B64</td> 757 901 </tr> 758 902 <tr> 759 903 <td>656 (0x290)</td> 904 <td>✓</td> 905 <td>✓</td> 760 906 <td>V_LSHRREV_B64</td> 761 907 </tr> 762 908 <tr> 763 909 <td>657 (0x291)</td> 910 <td>✓</td> 911 <td>✓</td> 764 912 <td>V_ASHRREV_I64</td> 765 913 </tr> 766 914 <tr> 767 915 <td>658 (0x292)</td> 916 <td>✓</td> 917 <td>✓</td> 768 918 <td>V_TRIG_PREOP_F64</td> 769 919 </tr> 770 920 <tr> 771 921 <td>659 (0x293)</td> 922 <td>✓</td> 923 <td>✓</td> 772 924 <td>V_BFM_B32</td> 773 925 </tr> 774 926 <tr> 775 927 <td>660 (0x294)</td> 928 <td>✓</td> 929 <td>✓</td> 776 930 <td>V_CVT_PKNORM_I16_F32</td> 777 931 </tr> 778 932 <tr> 779 933 <td>661 (0x295)</td> 934 <td>✓</td> 935 <td>✓</td> 780 936 <td>V_CVT_PKNORM_U16_F32</td> 781 937 </tr> 782 938 <tr> 783 939 <td>662 (0x296)</td> 940 <td>✓</td> 941 <td>✓</td> 784 942 <td>V_CVT_PKRTZ_F16_F32</td> 785 943 </tr> 786 944 <tr> 787 945 <td>663 (0x297)</td> 946 <td>✓</td> 947 <td>✓</td> 788 948 <td>V_CVT_PK_U16_U32</td> 789 949 </tr> 790 950 <tr> 791 951 <td>664 (0x298)</td> 952 <td>✓</td> 953 <td>✓</td> 792 954 <td>V_CVT_PK_I16_I32</td> 955 </tr> 956 <tr> 957 <td>665 (0x299)</td> 958 <td></td> 959 <td>✓</td> 960 <td>V_CVT_PKNORM_I16_F16</td> 961 </tr> 962 <tr> 963 <td>666 (0x29a)</td> 964 <td></td> 965 <td>✓</td> 966 <td>V_CVT_PKNORM_U16_F16</td> 793 967 </tr> 794 968 </tbody> … … 987 1161 VAL8 = (UINT8)MAX(MIN(f, 255.0), 0.0) 988 1162 VDST = (VDST&~mask) | (((UINT32)VAL8) << shift)</code></p> 1163 <h4>V_CVT_PKNORM_I16_F16</h4> 1164 <p>Opcode: 665 (0x299) for GCN 1.4<br /> 1165 Syntax: V_CVT_PKNORM_I16_F16 VDST, SRC0, SRC1<br /> 1166 Description: Convert normalized half FP value from SRC0 and SRC1 to 1167 signed 16-bit integers with rounding to nearest to even (??), 1168 and store first value to low 16-bit and second to high 16-bit of the VDST.<br /> 1169 Operation:<br /> 1170 <code>INT16 roundNorm(HALF S) 1171 { 1172 FLOAT f = RNDNEINT(S*32767) 1173 if (ISNAN(f)) 1174 return 0 1175 return (INT16)MAX(MIN(f, 32767.0), -32767.0) 1176 } 1177 VDST = roundNorm(ASHALF(SRC0)) | ((UINT32)roundNorm(ASHALF(SRC1)) << 16)</code></p> 989 1178 <h4>V_CVT_PKNORM_I16_F32</h4> 990 1179 <p>Opcode: 660 (0x294) for GCN 1.2<br /> … … 1002 1191 } 1003 1192 VDST = roundNorm(ASFLOAT(SRC0)) | ((UINT32)roundNorm(ASFLOAT(SRC1)) << 16)</code></p> 1193 <h4>V_CVT_PKNORM_U16_F16</h4> 1194 <p>Opcode: 666 (0x29a) for GCN 1.4<br /> 1195 Syntax: V_CVT_PKNORM_U16_F16 VDST, SRC0, SRC1<br /> 1196 Description: Convert normalized half FP value from SRC0 and SRC1 to 1197 unsigned 16-bit integers with rounding to nearest to even (??), 1198 and store first value to low 16-bit and second to high 16-bit of the VDST.<br /> 1199 Operation:<br /> 1200 <code>UINT16 roundNorm(HALF S) 1201 { 1202 HALF f = RNDNEINT(S*65535.0) 1203 if (ISNAN(f)) 1204 return 0 1205 return (INT16)MAX(MIN(f, 65535.0), 0.0) 1206 } 1207 VDST = roundNorm(ASHALF(SRC0)) | ((UINT32)roundNorm(ASHALF(SRC1)) << 16)</code></p> 1004 1208 <h4>V_CVT_PKNORM_U16_F32</h4> 1005 1209 <p>Opcode: 661 (0x295) for GCN 1.2<br />