Changes between Version 38 and Version 39 of GcnInstrsVop3


Ignore:
Timestamp:
12/02/17 19:00:28 (6 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GcnInstrsVop3

    v38 v39  
    885885</tr>
    886886<tr>
    887 <td>627 (0x273)</td>
     887<td>628 (0x274)</td>
    888888<td>V_INTERP_P1LL_F16 (VINTRP)</td>
    889889<td>V_INTERP_P1LL_F16 (VINTRP)</td>
    890890</tr>
    891891<tr>
    892 <td>628 (0x274)</td>
     892<td>629 (0x275)</td>
    893893<td>V_INTERP_P1LV_F16 (VINTRP)</td>
    894894<td>V_INTERP_P1LV_F16 (VINTRP)</td>
    895895</tr>
    896896<tr>
    897 <td>629 (0x275)</td>
     897<td>630 (0x276)</td>
    898898<td>V_INTERP_P2_F16 (VINTRP)</td>
     899<td>V_INTERP_P2_F16_LEGACY (VINTRP)</td>
     900</tr>
     901<tr>
     902<td>631 (0x277)</td>
     903<td>--</td>
    899904<td>V_INTERP_P2_F16 (VINTRP)</td>
    900905</tr>
     
    16131618<code>// SRC0*SRC1+SRC2
    16141619VDST = FMA(ASHALF(SRC0), ASHALF(SRC1), ASHALF(SRC2))</code></p>
    1615 <h4>V_INTERP_P1_F32</h4>
    1616 <p>Opcode: 624 (0x270) for GCN 1.2/1.4<br />
    1617 Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br />
    1618 Description: Instruction does the first step of the interpolation (P0 + P10*I). The I
    1619 coordinate given in VSRC register.<br />
    1620 NOTE: The indices in LDS is dword indices.<br />
    1621 NOTE: VDST and VSRC registers must not be same.<br />
    1622 Operation:<br />
    1623 <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
    1624 FLOAT P0[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2])
    1625 FLOAT P10[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2 + 1])
    1626 VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p>
    1627 <h4>V_INTERP_P2_F32</h4>
    1628 <p>Opcode: 625 (0x271) for GCN 1.2/1.4<br />
    1629 Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br />
    1630 Description: Instruction does the second step of the interpolation (P20*J + D). The J
    1631 coordinate given in VSRC register.<br />
    1632 NOTE: The indices in LDS is dword indices.<br />
    1633 NOTE: VDST and VSRC registers must not be same.<br />
    1634 Operation:<br />
    1635 <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
    1636 FLOAT P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8])
    1637 VDST[LANEID] = ASFLOAT(VDST[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p>
    16381620<h4>V_INTERP_MOV_F32</h4>
    16391621<p>Opcode: 626 (0x272) for GCN 1.2/1.4<br />
    16401622Syntax: V_INTERP_MOV_F32 VDST, PARAMTYPE, ATTR.ATTRCHAN<br />
    1641 Description: Move parameter value into VDST. The PARAMTYPE is P0, P10 or P20.<br />
     1623Description: Move parameter value into VDST. The PARAMTYPE is P0, P10 or P20.
     1624Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
    16421625NOTE: The indices in LDS is dword indices.<br />
    16431626Operation:<br />
     
    16491632else if (PARAMTYPE==P20)
    16501633    VDST[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8])</code></p>
     1634<h4>V_INTERP_P1_F32</h4>
     1635<p>Opcode: 624 (0x270) for GCN 1.2/1.4<br />
     1636Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br />
     1637Description: Instruction does the first step of the interpolation (P0 + P10*I). The I
     1638coordinate given in VSRC register. Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1639NOTE: The indices in LDS is dword indices.<br />
     1640NOTE: VDST and VSRC registers must not be same.<br />
     1641Operation:<br />
     1642<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1643FLOAT P0[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2])
     1644FLOAT P10[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2 + 1])
     1645VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p>
     1646<h4>V_INTERP_P1LL_F16</h4>
     1647<p>Opcode: 628 (0x274) for GCN 1.2/1.4<br />
     1648Syntax: V_INTERP_P1LL_F16 VDST, VSRC, ATTR.ATTRCHAN [HIGH]<br />
     1649Description: Instruction does the first step of the interpolation (P0 + P10*I). The I
     1650coordinate given in VSRC register. P0 and P10 factors are half floating point values stored
     1651in lower or higher (if 'HIGH' given) part of 32-bit dword.
     1652Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1653NOTE: The indices in LDS is dword indices.<br />
     1654NOTE: VDST and VSRC registers must not be same.<br />
     1655Operation:<br />
     1656<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1657HALF P0[LANEID], P10[LANEID]
     1658if (HIGH)
     1659{
     1660    P0[LANEID] = ASHALF(LDS[S + ATTRCHAN*2] &gt;&gt; 16)
     1661    P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] &gt;&gt; 16)
     1662}
     1663else
     1664{
     1665    P0[LANEID] = ASHALF(LDS[S + ATTRCHAN*2] &amp; 0xffff)
     1666    P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] &amp; 0xffff)
     1667}
     1668VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p>
     1669<h4>V_INTERP_P1LV_F16</h4>
     1670<p>Opcode: 629 (0x275) for GCN 1.2/1.4<br />
     1671Syntax: V_INTERP_P1LL_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br />
     1672Description: Instruction does the first step of the interpolation (P0 + P10*I). The I
     1673coordinate given in VSRC register. P10 and P0 factors are half floating point values stored
     1674in lower or higher (if 'HIGH' given) part of 32-bit dword. P0 is stored in VSRC1.
     1675Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1676NOTE: The indices in LDS is dword indices.<br />
     1677NOTE: VDST and VSRC registers must not be same.<br />
     1678Operation:<br />
     1679<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1680HALF P0[LANEID], P10[LANEID]
     1681if (HIGH)
     1682{
     1683    P0[LANEID] = ASHALF(VSRC1[LANEID] &gt;&gt; 16)
     1684    P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] &gt;&gt; 16)
     1685}
     1686else
     1687{
     1688    P0[LANEID] = ASHALF(VSRC1[LANEID] &amp; 0xffff)
     1689    P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] &amp; 0xffff)
     1690}
     1691VDST[LANEID] = P0 + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p>
     1692<h4>V_INTERP_P2_F32</h4>
     1693<p>Opcode: 625 (0x271) for GCN 1.2/1.4<br />
     1694Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br />
     1695Description: Instruction does the second step of the interpolation (P20*J + D). The J
     1696coordinate given in VSRC register. Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1697NOTE: The indices in LDS is dword indices.<br />
     1698NOTE: VDST and VSRC registers must not be same.<br />
     1699Operation:<br />
     1700<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1701FLOAT P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8])
     1702VDST[LANEID] = ASFLOAT(VDST[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p>
     1703<h4>V_INTERP_P2_F16 (GCN 1.2)</h4>
     1704<p>Opcode: 630 (0x276) for GCN 1.2/1.4<br />
     1705Syntax: V_INTERP_P1_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br />
     1706Syntax (GCN 1.4): V_INTERP_P1_F16_LEGACY VDST, VSRC, ATTR.ATTRCHAN [HIGH], VSRC1<br />
     1707Description: Instruction does the second step of the interpolation (P20*J + D). The J
     1708coordinate given in VSRC register. P2 factor is half floating point value stored in
     1709lower or higher (if HIGH given) part of dword.
     1710Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1711NOTE: The indices in LDS is dword indices.<br />
     1712NOTE: VDST and VSRC registers must not be same.<br />
     1713Operation:<br />
     1714<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1715HALF P20[LANEID]
     1716if (HIGH)
     1717    HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] &gt;&gt; 16)
     1718else
     1719    HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] &amp; 0xffff)
     1720VDST[LANEID] = ASFLOAT(VSRC1[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p>
     1721<h4>V_INTERP_P2_F16 (GCN 1.4)</h4>
     1722<p>Opcode: 631 (0x277) for GCN 1.4<br />
     1723Syntax: V_INTERP_P1_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br />
     1724Description: Instruction does the second step of the interpolation (P20*J + D). The J
     1725coordinate given in VSRC register. P2 factor is half floating point value stored in
     1726lower or higher (if HIGH given) part of dword.
     1727The 3-bit in OPSEL choose 16-bit part of destination (other part is preserved).
     1728Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br />
     1729NOTE: The indices in LDS is dword indices.<br />
     1730NOTE: VDST and VSRC registers must not be same.<br />
     1731Operation:<br />
     1732<code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID&gt;&gt;2))
     1733HALF P20[LANEID]
     1734if (HIGH)
     1735    HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] &gt;&gt; 16)
     1736else
     1737    HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] &amp; 0xffff)
     1738VDST[LANEID] = ASFLOAT(VSRC1[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p>
    16511739<h4>V_LDEXP_F32</h4>
    16521740<p>Opcode: 648 (0x288) for GCN 1.2/1.4<br />