1615 | | <h4>V_INTERP_P1_F32</h4> |
1616 | | <p>Opcode: 624 (0x270) for GCN 1.2/1.4<br /> |
1617 | | Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br /> |
1618 | | Description: Instruction does the first step of the interpolation (P0 + P10*I). The I |
1619 | | coordinate given in VSRC register.<br /> |
1620 | | NOTE: The indices in LDS is dword indices.<br /> |
1621 | | NOTE: VDST and VSRC registers must not be same.<br /> |
1622 | | Operation:<br /> |
1623 | | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
1624 | | FLOAT P0[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2]) |
1625 | | FLOAT P10[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2 + 1]) |
1626 | | VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p> |
1627 | | <h4>V_INTERP_P2_F32</h4> |
1628 | | <p>Opcode: 625 (0x271) for GCN 1.2/1.4<br /> |
1629 | | Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br /> |
1630 | | Description: Instruction does the second step of the interpolation (P20*J + D). The J |
1631 | | coordinate given in VSRC register.<br /> |
1632 | | NOTE: The indices in LDS is dword indices.<br /> |
1633 | | NOTE: VDST and VSRC registers must not be same.<br /> |
1634 | | Operation:<br /> |
1635 | | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
1636 | | FLOAT P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8]) |
1637 | | VDST[LANEID] = ASFLOAT(VDST[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p> |
| 1634 | <h4>V_INTERP_P1_F32</h4> |
| 1635 | <p>Opcode: 624 (0x270) for GCN 1.2/1.4<br /> |
| 1636 | Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br /> |
| 1637 | Description: Instruction does the first step of the interpolation (P0 + P10*I). The I |
| 1638 | coordinate given in VSRC register. Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1639 | NOTE: The indices in LDS is dword indices.<br /> |
| 1640 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1641 | Operation:<br /> |
| 1642 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1643 | FLOAT P0[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2]) |
| 1644 | FLOAT P10[LANEID] = ASFLOAT(LDS[S + ATTRCHAN*2 + 1]) |
| 1645 | VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p> |
| 1646 | <h4>V_INTERP_P1LL_F16</h4> |
| 1647 | <p>Opcode: 628 (0x274) for GCN 1.2/1.4<br /> |
| 1648 | Syntax: V_INTERP_P1LL_F16 VDST, VSRC, ATTR.ATTRCHAN [HIGH]<br /> |
| 1649 | Description: Instruction does the first step of the interpolation (P0 + P10*I). The I |
| 1650 | coordinate given in VSRC register. P0 and P10 factors are half floating point values stored |
| 1651 | in lower or higher (if 'HIGH' given) part of 32-bit dword. |
| 1652 | Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1653 | NOTE: The indices in LDS is dword indices.<br /> |
| 1654 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1655 | Operation:<br /> |
| 1656 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1657 | HALF P0[LANEID], P10[LANEID] |
| 1658 | if (HIGH) |
| 1659 | { |
| 1660 | P0[LANEID] = ASHALF(LDS[S + ATTRCHAN*2] >> 16) |
| 1661 | P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] >> 16) |
| 1662 | } |
| 1663 | else |
| 1664 | { |
| 1665 | P0[LANEID] = ASHALF(LDS[S + ATTRCHAN*2] & 0xffff) |
| 1666 | P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] & 0xffff) |
| 1667 | } |
| 1668 | VDST[LANEID] = P0[LANEID] + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p> |
| 1669 | <h4>V_INTERP_P1LV_F16</h4> |
| 1670 | <p>Opcode: 629 (0x275) for GCN 1.2/1.4<br /> |
| 1671 | Syntax: V_INTERP_P1LL_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br /> |
| 1672 | Description: Instruction does the first step of the interpolation (P0 + P10*I). The I |
| 1673 | coordinate given in VSRC register. P10 and P0 factors are half floating point values stored |
| 1674 | in lower or higher (if 'HIGH' given) part of 32-bit dword. P0 is stored in VSRC1. |
| 1675 | Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1676 | NOTE: The indices in LDS is dword indices.<br /> |
| 1677 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1678 | Operation:<br /> |
| 1679 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1680 | HALF P0[LANEID], P10[LANEID] |
| 1681 | if (HIGH) |
| 1682 | { |
| 1683 | P0[LANEID] = ASHALF(VSRC1[LANEID] >> 16) |
| 1684 | P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] >> 16) |
| 1685 | } |
| 1686 | else |
| 1687 | { |
| 1688 | P0[LANEID] = ASHALF(VSRC1[LANEID] & 0xffff) |
| 1689 | P10[LANEID] = ASHALF(LDS[S + ATTRCHAN*2 + 1] & 0xffff) |
| 1690 | } |
| 1691 | VDST[LANEID] = P0 + ASFLOAT(VSRC[LANEID]) * P10[LANEID]</code></p> |
| 1692 | <h4>V_INTERP_P2_F32</h4> |
| 1693 | <p>Opcode: 625 (0x271) for GCN 1.2/1.4<br /> |
| 1694 | Syntax: V_INTERP_P1_F32 VDST, VSRC, ATTR.ATTRCHAN<br /> |
| 1695 | Description: Instruction does the second step of the interpolation (P20*J + D). The J |
| 1696 | coordinate given in VSRC register. Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1697 | NOTE: The indices in LDS is dword indices.<br /> |
| 1698 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1699 | Operation:<br /> |
| 1700 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1701 | FLOAT P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8]) |
| 1702 | VDST[LANEID] = ASFLOAT(VDST[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p> |
| 1703 | <h4>V_INTERP_P2_F16 (GCN 1.2)</h4> |
| 1704 | <p>Opcode: 630 (0x276) for GCN 1.2/1.4<br /> |
| 1705 | Syntax: V_INTERP_P1_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br /> |
| 1706 | Syntax (GCN 1.4): V_INTERP_P1_F16_LEGACY VDST, VSRC, ATTR.ATTRCHAN [HIGH], VSRC1<br /> |
| 1707 | Description: Instruction does the second step of the interpolation (P20*J + D). The J |
| 1708 | coordinate given in VSRC register. P2 factor is half floating point value stored in |
| 1709 | lower or higher (if HIGH given) part of dword. |
| 1710 | Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1711 | NOTE: The indices in LDS is dword indices.<br /> |
| 1712 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1713 | Operation:<br /> |
| 1714 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1715 | HALF P20[LANEID] |
| 1716 | if (HIGH) |
| 1717 | HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] >> 16) |
| 1718 | else |
| 1719 | HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] & 0xffff) |
| 1720 | VDST[LANEID] = ASFLOAT(VSRC1[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p> |
| 1721 | <h4>V_INTERP_P2_F16 (GCN 1.4)</h4> |
| 1722 | <p>Opcode: 631 (0x277) for GCN 1.4<br /> |
| 1723 | Syntax: V_INTERP_P1_F16 VDST, VSRC, ATTR.ATTRCHAN, VSRC1 [HIGH]<br /> |
| 1724 | Description: Instruction does the second step of the interpolation (P20*J + D). The J |
| 1725 | coordinate given in VSRC register. P2 factor is half floating point value stored in |
| 1726 | lower or higher (if HIGH given) part of dword. |
| 1727 | The 3-bit in OPSEL choose 16-bit part of destination (other part is preserved). |
| 1728 | Refer to <a href="GcnInstrsVintrp">VINTRP instructions</a>.<br /> |
| 1729 | NOTE: The indices in LDS is dword indices.<br /> |
| 1730 | NOTE: VDST and VSRC registers must not be same.<br /> |
| 1731 | Operation:<br /> |
| 1732 | <code>UINT S = 12*(ATTR*NUMPRIM + PRIMID(LANEID>>2)) |
| 1733 | HALF P20[LANEID] |
| 1734 | if (HIGH) |
| 1735 | HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] >> 16) |
| 1736 | else |
| 1737 | HALF P20[LANEID] = ASFLOAT(LDS[S + ATTRCHAN + 8] & 0xffff) |
| 1738 | VDST[LANEID] = ASFLOAT(VSRC1[LANEID]) + ASFLOAT(VSRC[LANEID]) * P20[LANEID]</code></p> |