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AMD GCN Instruction Set Architecture

This chapter describes an instruction set of the GCN architecture, their addressing modes and features.

The GPU architectures differs significantly from CPU architectures. Main pressure in the GPU architectures is the parallelism and an efficient hiding memory latencies. The most CPU architectures provides an unified memory access approach. By contrast, the most GPU's have few different resource types for which access is different. Hence, few instruction's kinds: scalar, vector, main memory access instructions.

Instruction suffixes

Optionally, suffixes can be appended to instruction mnemonic to indicate encoding size. _e32 suffix marks that instruction will be encoded in single dword. _e64 suffix marks that instruction will be encoded in two dwords. _sdwa suffix marks that instruction uses SDWA encoding. _dpp suffix marks that instruction uses DPP encoding.

Language that describes operation.

In 'Operation' field, this document describes operation in specific computer language. This language is very similar to C/C++ and uses this same expresion's syntax (these same operators and their precedence). In this language, we use types there are to similar C/C++ types:

Special variables:

Special functions:

By default, any register value is treated as unsigned integer.



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