Changes between Version 15 and Version 16 of GcnOperands


Ignore:
Timestamp:
06/04/17 14:00:29 (7 years ago)
Author:
trac
Comment:

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  • GcnOperands

    v15 v16  
    382382<p>The HW registers and send message parameters (message and GSOP) is parametrizable if
    383383they will be preceded by <code>@</code> (example: <code>hwreg(@5, 8, 16)</code>).</p>
     384<h3>GPR indexing mode (GCN 1.2)</h3>
     385<p>The GCN 1.2 introduces the GPR indexing mode that facilitate usage of indexing in VGPR's.
     386The bit 27 in MODE register indicates whether this mode is enabled.
     387The M0 register holds index and mode of GPR indexing. If this mode will be enabled
     388then this index will be added to index of specified VGPR used in vector instruction.
     389The mode specifies to which operand of vector instruction GPR index will be added.
     390If sum of GPR index and VGPR register index beyond last available VGPR register or
     391this is not a VGPR register (SGPR or other), then operand register will be substituted by
     392V0 register.</p>
     393<p>The lowest 8 bits of M0 register holds the GPR index. The 12-15 bits holds GPR indexing mode.
     394The GPR indexing mode bits table:</p>
     395<table>
     396<thead>
     397<tr>
     398<th>Bit</th>
     399<th>Description</th>
     400</tr>
     401</thead>
     402<tbody>
     403<tr>
     404<td>0</td>
     405<td>Apply GPR indexing to VSRC0 operand</td>
     406</tr>
     407<tr>
     408<td>1</td>
     409<td>Apply GPR indexing to VSRC1 operand</td>
     410</tr>
     411<tr>
     412<td>2</td>
     413<td>Apply GPR indexing to VSRC2 operand</td>
     414</tr>
     415<tr>
     416<td>3</td>
     417<td>Apply GPR indexing to VDST operand</td>
     418</tr>
     419</tbody>
     420</table>
    384421}}}