Changes between Version 2 and Version 3 of GcnTimings


Ignore:
Timestamp:
01/26/16 00:00:15 (8 years ago)
Author:
trac
Comment:

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  • GcnTimings

    v2 v3  
    2121instruction outside these first 3 dwords adds single penalty.</li>
    2222<li>if instructions is longer (more than four cycles) then last cycles/4 dwords are free</li>
    23 <li>if 16 or more cycle 2-dword instruction and 2 dword insutrction in 4 dword, then
     23<li>if 16 or more cycle 2-dword instruction and 2 dword instruction in 4 dword, then
    2424no penalty for second 2-dword instruction.</li>
    2525</ul>
     26<h3>Instruction scheduling</h3>
     27<p>Between any vector operation that operates on VCC and any scalar ALU instruction is
     2816-cycle delay.</p>
    2629<h3>SOP2 Instruction timings</h3>
    2730<table>
    … …  
    368371</tbody>
    369372</table>
     373<h3>SOP1 Instruction timings</h3>
     374<p>The S_*_SAVEEXEC_B64 instructions takes 8 cycles. Other ALU instructions (expects
     375S_MOV_REGRD_B32, S_CBRANCH_JOIN, S_RFE_B64) take 4 cycles.</p>
     376<h3>SOPC Instruction timings</h3>
     377<p>All comparison and bit checking instructions take 4 cycles.</p>
    370378}}}